mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
drm/xe/display: Implement display support
As for display, the intent is to share the display code with the i915 driver so that there is maximum reuse there. We do this by recompiling i915/display code twice. Now that i915 has been adapted to support the Xe build, we can add the xe/display support. This initial work is a collaboration of many people and unfortunately this squashed patch won't fully honor the proper credits. But let's try to add a few from the squashed patches: Co-developed-by: Matthew Brost <matthew.brost@intel.com> Co-developed-by: Jani Nikula <jani.nikula@intel.com> Co-developed-by: Lucas De Marchi <lucas.demarchi@intel.com> Co-developed-by: Matt Roper <matthew.d.roper@intel.com> Co-developed-by: Mauro Carvalho Chehab <mchehab@kernel.org> Co-developed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Co-developed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Maarten Lankhorst
committed by
Rodrigo Vivi
Rodrigo Vivi
parent
a839e365ac
commit
44e694958b
@@ -6,6 +6,7 @@ CONFIG_DRM=y
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CONFIG_DRM_FBDEV_EMULATION=y
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CONFIG_DRM_KMS_HELPER=y
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CONFIG_DRM_XE=y
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CONFIG_DRM_XE_DISPLAY=n
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CONFIG_EXPERT=y
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CONFIG_FB=y
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CONFIG_DRM_XE_KUNIT_TEST=y
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@@ -12,8 +12,20 @@ config DRM_XE
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select DRM_KMS_HELPER
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select DRM_PANEL
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select DRM_SUBALLOC_HELPER
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select DRM_DISPLAY_DP_HELPER
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select DRM_DISPLAY_HDCP_HELPER
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select DRM_DISPLAY_HDMI_HELPER
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select DRM_DISPLAY_HELPER
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select DRM_MIPI_DSI
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select RELAY
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select IRQ_WORK
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# i915 depends on ACPI_VIDEO when ACPI is enabled
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# but for select to work, need to select ACPI_VIDEO's dependencies, ick
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select BACKLIGHT_CLASS_DEVICE if ACPI
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select INPUT if ACPI
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select ACPI_VIDEO if X86 && ACPI
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select ACPI_BUTTON if ACPI
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select ACPI_WMI if ACPI
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select SYNC_FILE
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select IOSF_MBI
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select CRC32
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@@ -33,6 +45,16 @@ config DRM_XE
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If "M" is selected, the module will be called xe.
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config DRM_XE_DISPLAY
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bool "Enable display support"
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depends on DRM_XE && EXPERT && DRM_XE=m
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select FB_IOMEM_HELPERS
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select I2C
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select I2C_ALGOBIT
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default y
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help
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Disable this option only if you want to compile out display support.
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config DRM_XE_FORCE_PROBE
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string "Force probe xe for selected Intel hardware IDs"
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depends on DRM_XE
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+136
-5
@@ -24,9 +24,6 @@ subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides)
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subdir-ccflags-y += $(call cc-disable-warning, frame-address)
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subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
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# Fine grained warnings disable
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CFLAGS_xe_pci.o = $(call cc-disable-warning, override-init)
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subdir-ccflags-y += -I$(obj) -I$(srctree)/$(src)
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# generated sources
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@@ -126,13 +123,147 @@ xe-y += xe_bb.o \
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# graphics hardware monitoring (HWMON) support
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xe-$(CONFIG_HWMON) += xe_hwmon.o
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obj-$(CONFIG_DRM_XE) += xe.o
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obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/
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# i915 Display compat #defines and #includes
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subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
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-I$(srctree)/$(src)/display/ext \
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-I$(srctree)/$(src)/compat-i915-headers \
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-I$(srctree)/drivers/gpu/drm/xe/display/ \
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-I$(srctree)/drivers/gpu/drm/i915/display/ \
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-Ddrm_i915_gem_object=xe_bo \
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-Ddrm_i915_private=xe_device
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CFLAGS_i915-display/intel_fbdev.o = $(call cc-disable-warning, override-init)
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CFLAGS_i915-display/intel_display_device.o = $(call cc-disable-warning, override-init)
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# Rule to build SOC code shared with i915
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$(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE
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$(call cmd,force_checksrc)
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$(call if_changed_rule,cc_o_c)
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# Rule to build display code shared with i915
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$(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
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$(call cmd,force_checksrc)
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$(call if_changed_rule,cc_o_c)
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# Display code specific to xe
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xe-$(CONFIG_DRM_XE_DISPLAY) += \
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xe_display.o \
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display/xe_fb_pin.o \
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display/xe_hdcp_gsc.o \
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display/xe_plane_initial.o \
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display/xe_display_rps.o \
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display/intel_fbdev_fb.o \
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display/intel_fb_bo.o \
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display/ext/i915_irq.o \
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display/ext/i915_utils.o
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# SOC code shared with i915
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xe-$(CONFIG_DRM_XE_DISPLAY) += \
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i915-soc/intel_dram.o \
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i915-soc/intel_pch.o
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# Display code shared with i915
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xe-$(CONFIG_DRM_XE_DISPLAY) += \
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i915-display/icl_dsi.o \
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i915-display/intel_atomic.o \
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i915-display/intel_atomic_plane.o \
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i915-display/intel_audio.o \
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i915-display/intel_backlight.o \
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i915-display/intel_bios.o \
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i915-display/intel_bw.o \
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i915-display/intel_cdclk.o \
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i915-display/intel_color.o \
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i915-display/intel_combo_phy.o \
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i915-display/intel_connector.o \
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i915-display/intel_crtc.o \
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i915-display/intel_crtc_state_dump.o \
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i915-display/intel_cursor.o \
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i915-display/intel_cx0_phy.o \
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i915-display/intel_ddi.o \
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i915-display/intel_ddi_buf_trans.o \
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i915-display/intel_display.o \
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i915-display/intel_display_debugfs.o \
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i915-display/intel_display_debugfs_params.o \
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i915-display/intel_display_device.o \
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i915-display/intel_display_driver.o \
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i915-display/intel_display_irq.o \
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i915-display/intel_display_params.o \
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i915-display/intel_display_power.o \
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i915-display/intel_display_power_map.o \
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i915-display/intel_display_power_well.o \
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i915-display/intel_display_trace.o \
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i915-display/intel_display_wa.o \
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i915-display/intel_dkl_phy.o \
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i915-display/intel_dmc.o \
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i915-display/intel_dp.o \
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i915-display/intel_dp_aux.o \
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i915-display/intel_dp_aux_backlight.o \
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i915-display/intel_dp_hdcp.o \
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i915-display/intel_dp_link_training.o \
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i915-display/intel_dp_mst.o \
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i915-display/intel_dpll.o \
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i915-display/intel_dpll_mgr.o \
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i915-display/intel_dpt_common.o \
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i915-display/intel_drrs.o \
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i915-display/intel_dsb.o \
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i915-display/intel_dsi.o \
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i915-display/intel_dsi_dcs_backlight.o \
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i915-display/intel_dsi_vbt.o \
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i915-display/intel_fb.o \
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i915-display/intel_fbc.o \
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i915-display/intel_fdi.o \
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i915-display/intel_fifo_underrun.o \
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i915-display/intel_frontbuffer.o \
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i915-display/intel_global_state.o \
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i915-display/intel_gmbus.o \
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i915-display/intel_hdcp.o \
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i915-display/intel_hdmi.o \
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i915-display/intel_hotplug.o \
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i915-display/intel_hotplug_irq.o \
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i915-display/intel_hti.o \
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i915-display/intel_link_bw.o \
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i915-display/intel_lspcon.o \
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i915-display/intel_modeset_lock.o \
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i915-display/intel_modeset_setup.o \
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i915-display/intel_modeset_verify.o \
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i915-display/intel_panel.o \
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i915-display/intel_pipe_crc.o \
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i915-display/intel_pmdemand.o \
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i915-display/intel_pps.o \
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i915-display/intel_psr.o \
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i915-display/intel_qp_tables.o \
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i915-display/intel_quirks.o \
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i915-display/intel_snps_phy.o \
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i915-display/intel_tc.o \
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i915-display/intel_vblank.o \
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i915-display/intel_vdsc.o \
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i915-display/intel_vga.o \
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i915-display/intel_vrr.o \
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i915-display/intel_wm.o \
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i915-display/skl_scaler.o \
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i915-display/skl_universal_plane.o \
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i915-display/skl_watermark.o
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xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
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ifeq ($(CONFIG_ACPI),y)
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xe-$(CONFIG_DRM_XE_DISPLAY) += \
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i915-display/intel_acpi.o \
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i915-display/intel_opregion.o
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endif
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ifeq ($(CONFIG_DRM_FBDEV_EMULATION),y)
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xe-$(CONFIG_DRM_XE_DISPLAY) += i915-display/intel_fbdev.o
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endif
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obj-$(CONFIG_DRM_XE) += xe.o
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obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/
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# header test
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hdrtest_find_args := -not -path xe_rtp_helpers.h
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ifneq ($(CONFIG_DRM_XE_DISPLAY),y)
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hdrtest_find_args += -not -path display/\* -not -path compat-i915-headers/\* -not -path xe_display.h
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endif
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always-$(CONFIG_DRM_XE_WERROR) += \
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$(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) && find * -name '*.h' $(hdrtest_find_args)))
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@@ -0,0 +1 @@
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/* Empty */
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _I915_GEM_MMAN_H_
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#define _I915_GEM_MMAN_H_
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#include "xe_bo_types.h"
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#include <drm/drm_prime.h>
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static inline int i915_gem_fb_mmap(struct xe_bo *bo, struct vm_area_struct *vma)
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{
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return drm_gem_prime_mmap(&bo->ttm.base, vma);
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}
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#endif
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@@ -0,0 +1,65 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _I915_GEM_OBJECT_H_
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#define _I915_GEM_OBJECT_H_
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#include <linux/types.h>
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#include "xe_bo.h"
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#define i915_gem_object_is_shmem(obj) ((obj)->flags & XE_BO_CREATE_SYSTEM_BIT)
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static inline dma_addr_t i915_gem_object_get_dma_address(const struct xe_bo *bo, pgoff_t n)
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{
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/* Should never be called */
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WARN_ON(1);
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return n;
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}
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static inline bool i915_gem_object_is_tiled(const struct xe_bo *bo)
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{
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/* legacy tiling is unused */
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return false;
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}
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static inline bool i915_gem_object_is_userptr(const struct xe_bo *bo)
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{
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/* legacy tiling is unused */
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return false;
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}
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static inline int i915_gem_object_read_from_page(struct xe_bo *bo,
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u32 ofs, u64 *ptr, u32 size)
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{
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struct ttm_bo_kmap_obj map;
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void *virtual;
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bool is_iomem;
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int ret;
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XE_WARN_ON(size != 8);
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ret = xe_bo_lock(bo, true);
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if (ret)
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return ret;
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ret = ttm_bo_kmap(&bo->ttm, ofs >> PAGE_SHIFT, 1, &map);
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if (ret)
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goto out_unlock;
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ofs &= ~PAGE_MASK;
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virtual = ttm_kmap_obj_virtual(&map, &is_iomem);
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if (is_iomem)
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*ptr = readq((void __iomem *)(virtual + ofs));
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else
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*ptr = *(u64 *)(virtual + ofs);
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ttm_bo_kunmap(&map);
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out_unlock:
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xe_bo_unlock(bo);
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return ret;
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}
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#endif
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@@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_RPS_H__
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#define __INTEL_RPS_H__
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#define gen5_rps_irq_handler(x) ({})
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#endif /* __INTEL_RPS_H__ */
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@@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __I915_CONFIG_H__
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#define __I915_CONFIG_H__
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#include <linux/sched.h>
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struct drm_i915_private;
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static inline unsigned long
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i915_fence_timeout(const struct drm_i915_private *i915)
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{
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return MAX_SCHEDULE_TIMEOUT;
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}
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#endif /* __I915_CONFIG_H__ */
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@@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __I915_DEBUGFS_H__
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#define __I915_DEBUGFS_H__
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struct drm_i915_gem_object;
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struct seq_file;
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static inline void i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) {}
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#endif /* __I915_DEBUGFS_H__ */
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@@ -0,0 +1,230 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_I915_DRV_H_
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#define _XE_I915_DRV_H_
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/*
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* "Adaptation header" to allow i915 display to also build for xe driver.
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* TODO: refactor i915 and xe so this can cease to exist
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*/
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#include <drm/drm_drv.h>
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#include "gem/i915_gem_object.h"
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#include "soc/intel_pch.h"
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#include "xe_device.h"
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#include "xe_bo.h"
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#include "xe_pm.h"
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#include "xe_step.h"
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#include "i915_gpu_error.h"
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#include "i915_reg_defs.h"
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#include "i915_utils.h"
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#include "intel_step.h"
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#include "intel_uc_fw.h"
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#include "intel_uncore.h"
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#include "intel_runtime_pm.h"
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#include <linux/pm_runtime.h>
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static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
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{
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return container_of(dev, struct drm_i915_private, drm);
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}
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static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
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{
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return dev_get_drvdata(kdev);
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}
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#define INTEL_JASPERLAKE 0
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#define INTEL_ELKHARTLAKE 0
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#define IS_PLATFORM(xe, x) ((xe)->info.platform == x)
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#define INTEL_INFO(dev_priv) (&((dev_priv)->info))
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#define INTEL_DEVID(dev_priv) ((dev_priv)->info.devid)
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#define IS_I830(dev_priv) (dev_priv && 0)
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#define IS_I845G(dev_priv) (dev_priv && 0)
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#define IS_I85X(dev_priv) (dev_priv && 0)
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#define IS_I865G(dev_priv) (dev_priv && 0)
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#define IS_I915G(dev_priv) (dev_priv && 0)
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#define IS_I915GM(dev_priv) (dev_priv && 0)
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#define IS_I945G(dev_priv) (dev_priv && 0)
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#define IS_I945GM(dev_priv) (dev_priv && 0)
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#define IS_I965G(dev_priv) (dev_priv && 0)
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#define IS_I965GM(dev_priv) (dev_priv && 0)
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#define IS_G45(dev_priv) (dev_priv && 0)
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#define IS_GM45(dev_priv) (dev_priv && 0)
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#define IS_G4X(dev_priv) (dev_priv && 0)
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#define IS_PINEVIEW(dev_priv) (dev_priv && 0)
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#define IS_G33(dev_priv) (dev_priv && 0)
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#define IS_IRONLAKE(dev_priv) (dev_priv && 0)
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#define IS_IRONLAKE_M(dev_priv) (dev_priv && 0)
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#define IS_SANDYBRIDGE(dev_priv) (dev_priv && 0)
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#define IS_IVYBRIDGE(dev_priv) (dev_priv && 0)
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#define IS_IVB_GT1(dev_priv) (dev_priv && 0)
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#define IS_VALLEYVIEW(dev_priv) (dev_priv && 0)
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#define IS_CHERRYVIEW(dev_priv) (dev_priv && 0)
|
||||
#define IS_HASWELL(dev_priv) (dev_priv && 0)
|
||||
#define IS_BROADWELL(dev_priv) (dev_priv && 0)
|
||||
#define IS_SKYLAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_BROXTON(dev_priv) (dev_priv && 0)
|
||||
#define IS_KABYLAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_GEMINILAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_COFFEELAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_COMETLAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_ICELAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_JASPERLAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_ELKHARTLAKE(dev_priv) (dev_priv && 0)
|
||||
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_TIGERLAKE)
|
||||
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_ROCKETLAKE)
|
||||
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
|
||||
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
|
||||
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
|
||||
#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
|
||||
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
|
||||
#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
|
||||
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
|
||||
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
|
||||
|
||||
#define IS_HASWELL_ULT(dev_priv) (dev_priv && 0)
|
||||
#define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0)
|
||||
#define IS_BROADWELL_ULX(dev_priv) (dev_priv && 0)
|
||||
|
||||
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
|
||||
|
||||
#define INTEL_DISPLAY_ENABLED(xe) (HAS_DISPLAY((xe)) && !intel_opregion_headless_sku((xe)))
|
||||
|
||||
#define IS_GRAPHICS_VER(xe, first, last) \
|
||||
((xe)->info.graphics_verx100 >= first * 100 && \
|
||||
(xe)->info.graphics_verx100 <= (last*100 + 99))
|
||||
#define IS_MOBILE(xe) (xe && 0)
|
||||
#define HAS_LLC(xe) (!IS_DGFX((xe)))
|
||||
|
||||
#define HAS_GMD_ID(xe) GRAPHICS_VERx100(xe) >= 1270
|
||||
|
||||
/* Workarounds not handled yet */
|
||||
#define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)->info.step.display; first <= __step && __step <= last; })
|
||||
#define IS_GRAPHICS_STEP(xe, first, last) ({u8 __step = (xe)->info.step.graphics; first <= __step && __step <= last; })
|
||||
|
||||
#define IS_LP(xe) (0)
|
||||
#define IS_GEN9_LP(xe) (0)
|
||||
#define IS_GEN9_BC(xe) (0)
|
||||
|
||||
#define IS_TIGERLAKE_UY(xe) (xe && 0)
|
||||
#define IS_COMETLAKE_ULX(xe) (xe && 0)
|
||||
#define IS_COFFEELAKE_ULX(xe) (xe && 0)
|
||||
#define IS_KABYLAKE_ULX(xe) (xe && 0)
|
||||
#define IS_SKYLAKE_ULX(xe) (xe && 0)
|
||||
#define IS_HASWELL_ULX(xe) (xe && 0)
|
||||
#define IS_COMETLAKE_ULT(xe) (xe && 0)
|
||||
#define IS_COFFEELAKE_ULT(xe) (xe && 0)
|
||||
#define IS_KABYLAKE_ULT(xe) (xe && 0)
|
||||
#define IS_SKYLAKE_ULT(xe) (xe && 0)
|
||||
|
||||
#define IS_DG1_GRAPHICS_STEP(xe, first, last) (IS_DG1(xe) && IS_GRAPHICS_STEP(xe, first, last))
|
||||
#define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
|
||||
((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
|
||||
IS_GRAPHICS_STEP(xe, first, last))
|
||||
#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last))
|
||||
|
||||
/* XXX: No basedie stepping support yet */
|
||||
#define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
|
||||
|
||||
#define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last) (IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
#define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last) (IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
#define IS_DG1_DISPLAY_STEP(xe, first, last) (IS_DG1(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
#define IS_DG2_DISPLAY_STEP(xe, first, last) (IS_DG2(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
#define IS_ADLP_DISPLAY_STEP(xe, first, last) (IS_ALDERLAKE_P(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
#define IS_ADLS_DISPLAY_STEP(xe, first, last) (IS_ALDERLAKE_S(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
#define IS_JSL_EHL_DISPLAY_STEP(xe, first, last) (IS_JSL_EHL(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
#define IS_MTL_DISPLAY_STEP(xe, first, last) (IS_METEORLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
|
||||
/* FIXME: Add subplatform here */
|
||||
#define IS_MTL_GRAPHICS_STEP(xe, sub, first, last) (IS_METEORLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
|
||||
|
||||
#define IS_DG2_G10(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G10)
|
||||
#define IS_DG2_G11(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G11)
|
||||
#define IS_DG2_G12(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G12)
|
||||
#define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU)
|
||||
#define IS_ICL_WITH_PORT_F(xe) (xe && 0)
|
||||
#define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe))
|
||||
#define to_intel_bo(x) gem_to_xe_bo((x))
|
||||
#define mkwrite_device_info(xe) (INTEL_INFO(xe))
|
||||
|
||||
#define HAS_128_BYTE_Y_TILING(xe) (xe || 1)
|
||||
|
||||
#define intel_has_gpu_reset(a) (a && 0)
|
||||
|
||||
#include "intel_wakeref.h"
|
||||
|
||||
static inline bool intel_runtime_pm_get(struct xe_runtime_pm *pm)
|
||||
{
|
||||
struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
|
||||
|
||||
if (xe_pm_runtime_get(xe) < 0) {
|
||||
xe_pm_runtime_put(xe);
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool intel_runtime_pm_get_if_in_use(struct xe_runtime_pm *pm)
|
||||
{
|
||||
struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
|
||||
|
||||
return xe_pm_runtime_get_if_active(xe);
|
||||
}
|
||||
|
||||
static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm)
|
||||
{
|
||||
struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
|
||||
|
||||
xe_pm_runtime_put(xe);
|
||||
}
|
||||
|
||||
static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm, bool wakeref)
|
||||
{
|
||||
if (wakeref)
|
||||
intel_runtime_pm_put_unchecked(pm);
|
||||
}
|
||||
|
||||
#define intel_runtime_pm_get_raw intel_runtime_pm_get
|
||||
#define intel_runtime_pm_put_raw intel_runtime_pm_put
|
||||
#define assert_rpm_wakelock_held(x) do { } while (0)
|
||||
#define assert_rpm_raw_wakeref_held(x) do { } while (0)
|
||||
|
||||
#define intel_uncore_forcewake_get(x, y) do { } while (0)
|
||||
#define intel_uncore_forcewake_put(x, y) do { } while (0)
|
||||
|
||||
#define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0)
|
||||
|
||||
#define I915_PRIORITY_DISPLAY 0
|
||||
struct i915_sched_attr {
|
||||
int priority;
|
||||
};
|
||||
#define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0)
|
||||
|
||||
#define with_intel_runtime_pm(rpm, wf) \
|
||||
for ((wf) = intel_runtime_pm_get(rpm); (wf); \
|
||||
intel_runtime_pm_put((rpm), (wf)), (wf) = 0)
|
||||
|
||||
#define pdev_to_i915 pdev_to_xe_device
|
||||
#define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime)
|
||||
|
||||
#define FORCEWAKE_ALL XE_FORCEWAKE_ALL
|
||||
#define HPD_STORM_DEFAULT_THRESHOLD 50
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
/*
|
||||
* arm64 indirectly includes linux/rtc.h,
|
||||
* which defines a irq_lock, so include it
|
||||
* here before #define-ing it
|
||||
*/
|
||||
#include <linux/rtc.h>
|
||||
#endif
|
||||
|
||||
#define irq_lock irq.lock
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,6 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#include "../../i915/i915_fixed.h"
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef _I915_GPU_ERROR_H_
|
||||
#define _I915_GPU_ERROR_H_
|
||||
|
||||
struct drm_i915_error_state_buf;
|
||||
|
||||
__printf(2, 3)
|
||||
static inline void
|
||||
i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,6 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#include "../../i915/i915_irq.h"
|
||||
@@ -0,0 +1,6 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#include "../../i915/i915_reg.h"
|
||||
@@ -0,0 +1,6 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#include "../../i915/i915_reg_defs.h"
|
||||
@@ -0,0 +1,6 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#define trace_i915_reg_rw(a...) do { } while (0)
|
||||
@@ -0,0 +1,6 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#include "../../i915/i915_utils.h"
|
||||
@@ -0,0 +1,44 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef _I915_VGPU_H_
|
||||
#define _I915_VGPU_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct drm_i915_private;
|
||||
struct i915_ggtt;
|
||||
|
||||
static inline void intel_vgpu_detect(struct drm_i915_private *i915)
|
||||
{
|
||||
}
|
||||
static inline bool intel_vgpu_active(struct drm_i915_private *i915)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline void intel_vgpu_register(struct drm_i915_private *i915)
|
||||
{
|
||||
}
|
||||
static inline bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *i915)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *i915)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline bool intel_vgpu_has_huge_gtt(struct drm_i915_private *i915)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline int intel_vgt_balloon(struct i915_ggtt *ggtt)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void intel_vgt_deballoon(struct i915_ggtt *ggtt)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* _I915_VGPU_H_ */
|
||||
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2023 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef I915_VMA_H
|
||||
#define I915_VMA_H
|
||||
|
||||
#include <uapi/drm/i915_drm.h>
|
||||
#include <drm/drm_mm.h>
|
||||
|
||||
/* We don't want these from i915_drm.h in case of Xe */
|
||||
#undef I915_TILING_X
|
||||
#undef I915_TILING_Y
|
||||
#define I915_TILING_X 0
|
||||
#define I915_TILING_Y 0
|
||||
|
||||
struct xe_bo;
|
||||
|
||||
struct i915_vma {
|
||||
struct xe_bo *bo, *dpt;
|
||||
struct drm_mm_node node;
|
||||
};
|
||||
|
||||
|
||||
static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
|
||||
{
|
||||
return vma->node.start;
|
||||
}
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user