mirror of
https://github.com/linux-msm/laptops-kernel.git
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sh: remove sh5 support
sh5 never became a product and has probably never really worked. Remove it by recursively deleting all associated Kconfig options and all corresponding files. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rich Felker <dalias@libc.org>
This commit is contained in:
Arnd Bergmann
committed by
Rich Felker
Rich Felker
parent
d1f56f318d
commit
37744feebc
+10
-52
@@ -54,15 +54,6 @@ config SUPERH
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select HAVE_NMI
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select HAVE_NMI
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select NEED_SG_DMA_LENGTH
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select NEED_SG_DMA_LENGTH
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select ARCH_HAS_GIGANTIC_PAGE
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select ARCH_HAS_GIGANTIC_PAGE
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help
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The SuperH is a RISC processor targeted for use in embedded systems
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and consumer electronics; it was also used in the Sega Dreamcast
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gaming console. The SuperH port has a home page at
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<http://www.linux-sh.org/>.
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config SUPERH32
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def_bool "$(ARCH)" = "sh"
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select ARCH_32BIT_OFF_T
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select ARCH_32BIT_OFF_T
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select GUP_GET_PTE_LOW_HIGH if X2TLB
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select GUP_GET_PTE_LOW_HIGH if X2TLB
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select HAVE_KPROBES
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select HAVE_KPROBES
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@@ -81,19 +72,15 @@ config SUPERH32
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select ARCH_HIBERNATION_POSSIBLE if MMU
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select ARCH_HIBERNATION_POSSIBLE if MMU
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select SPARSE_IRQ
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select SPARSE_IRQ
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select HAVE_STACKPROTECTOR
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select HAVE_STACKPROTECTOR
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help
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config SUPERH64
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The SuperH is a RISC processor targeted for use in embedded systems
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def_bool "$(ARCH)" = "sh64"
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and consumer electronics; it was also used in the Sega Dreamcast
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select HAVE_EXIT_THREAD
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gaming console. The SuperH port has a home page at
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select KALLSYMS
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<http://www.linux-sh.org/>.
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config GENERIC_BUG
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config GENERIC_BUG
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def_bool y
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def_bool y
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depends on BUG && SUPERH32
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depends on BUG
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config GENERIC_CSUM
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def_bool y
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depends on SUPERH64
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config GENERIC_HWEIGHT
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config GENERIC_HWEIGHT
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def_bool y
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def_bool y
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@@ -203,12 +190,6 @@ config CPU_SH4AL_DSP
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select CPU_SH4A
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select CPU_SH4A
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select CPU_HAS_DSP
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select CPU_HAS_DSP
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config CPU_SH5
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bool
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select CPU_HAS_FPU
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select SYS_SUPPORTS_SH_TMU
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select SYS_SUPPORTS_HUGETLBFS if MMU
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config CPU_SHX2
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config CPU_SHX2
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bool
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bool
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@@ -228,8 +209,6 @@ config CPU_HAS_PMU
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default y
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default y
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bool
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bool
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if SUPERH32
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choice
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choice
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prompt "Processor sub-type selection"
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prompt "Processor sub-type selection"
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@@ -518,27 +497,6 @@ config CPU_SUBTYPE_SH7366
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endchoice
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endchoice
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endif
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if SUPERH64
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choice
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prompt "Processor sub-type selection"
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# SH-5 Processor Support
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config CPU_SUBTYPE_SH5_101
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bool "Support SH5-101 processor"
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select CPU_SH5
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config CPU_SUBTYPE_SH5_103
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bool "Support SH5-103 processor"
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select CPU_SH5
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endchoice
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endif
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source "arch/sh/mm/Kconfig"
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source "arch/sh/mm/Kconfig"
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source "arch/sh/Kconfig.cpu"
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source "arch/sh/Kconfig.cpu"
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@@ -592,7 +550,7 @@ source "kernel/Kconfig.hz"
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config KEXEC
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config KEXEC
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bool "kexec system call (EXPERIMENTAL)"
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bool "kexec system call (EXPERIMENTAL)"
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depends on SUPERH32 && MMU
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depends on MMU
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select KEXEC_CORE
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select KEXEC_CORE
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help
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help
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kexec is a system call that implements the ability to shutdown your
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kexec is a system call that implements the ability to shutdown your
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@@ -610,7 +568,7 @@ config KEXEC
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config CRASH_DUMP
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config CRASH_DUMP
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bool "kernel crash dumps (EXPERIMENTAL)"
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bool "kernel crash dumps (EXPERIMENTAL)"
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depends on SUPERH32 && BROKEN_ON_SMP
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depends on BROKEN_ON_SMP
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help
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help
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Generate crash dump after being started by kexec.
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Generate crash dump after being started by kexec.
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This should be normally only set in special crash dump kernels
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This should be normally only set in special crash dump kernels
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@@ -624,7 +582,7 @@ config CRASH_DUMP
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config KEXEC_JUMP
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config KEXEC_JUMP
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bool "kexec jump (EXPERIMENTAL)"
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bool "kexec jump (EXPERIMENTAL)"
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depends on SUPERH32 && KEXEC && HIBERNATION
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depends on KEXEC && HIBERNATION
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help
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help
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Jump between original kernel and kexeced kernel and invoke
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Jump between original kernel and kexeced kernel and invoke
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code via KEXEC
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code via KEXEC
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@@ -701,7 +659,7 @@ config HOTPLUG_CPU
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config GUSA
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config GUSA
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def_bool y
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def_bool y
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depends on !SMP && SUPERH32
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depends on !SMP
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help
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help
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This enables support for gUSA (general UserSpace Atomicity).
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This enables support for gUSA (general UserSpace Atomicity).
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This is the default implementation for both UP and non-ll/sc
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This is the default implementation for both UP and non-ll/sc
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@@ -13,7 +13,6 @@ config CPU_LITTLE_ENDIAN
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config CPU_BIG_ENDIAN
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config CPU_BIG_ENDIAN
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bool "Big Endian"
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bool "Big Endian"
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depends on !CPU_SH5
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endchoice
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endchoice
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@@ -27,10 +26,6 @@ config SH_FPU
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This option must be set in order to enable the FPU.
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This option must be set in order to enable the FPU.
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config SH64_FPU_DENORM_FLUSH
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bool "Flush floating point denorms to zero"
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depends on SH_FPU && SUPERH64
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config SH_FPU_EMU
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config SH_FPU_EMU
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def_bool n
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def_bool n
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prompt "FPU emulation support"
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prompt "FPU emulation support"
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@@ -77,10 +72,6 @@ config SPECULATIVE_EXECUTION
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If unsure, say N.
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If unsure, say N.
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config SH64_ID2815_WORKAROUND
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bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
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depends on CPU_SUBTYPE_SH5_101
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config CPU_HAS_INTEVT
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config CPU_HAS_INTEVT
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bool
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bool
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+3
-10
@@ -5,7 +5,6 @@ config TRACE_IRQFLAGS_SUPPORT
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config SH_STANDARD_BIOS
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config SH_STANDARD_BIOS
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bool "Use LinuxSH standard BIOS"
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bool "Use LinuxSH standard BIOS"
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depends on SUPERH32
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help
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help
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Say Y here if your target has the gdb-sh-stub
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Say Y here if your target has the gdb-sh-stub
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package from www.m17n.org (or any conforming standard LinuxSH BIOS)
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package from www.m17n.org (or any conforming standard LinuxSH BIOS)
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@@ -19,7 +18,7 @@ config SH_STANDARD_BIOS
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config STACK_DEBUG
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config STACK_DEBUG
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bool "Check for stack overflows"
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bool "Check for stack overflows"
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depends on DEBUG_KERNEL && SUPERH32
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depends on DEBUG_KERNEL
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help
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help
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This option will cause messages to be printed if free stack space
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This option will cause messages to be printed if free stack space
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drops below a certain limit. Saying Y here will add overhead to
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drops below a certain limit. Saying Y here will add overhead to
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@@ -38,7 +37,7 @@ config 4KSTACKS
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config IRQSTACKS
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config IRQSTACKS
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bool "Use separate kernel stacks when processing interrupts"
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bool "Use separate kernel stacks when processing interrupts"
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depends on DEBUG_KERNEL && SUPERH32 && BROKEN
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depends on DEBUG_KERNEL && BROKEN
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help
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help
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If you say Y here the kernel will use separate kernel stacks
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If you say Y here the kernel will use separate kernel stacks
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for handling hard and soft interrupts. This can help avoid
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for handling hard and soft interrupts. This can help avoid
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@@ -46,7 +45,7 @@ config IRQSTACKS
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config DUMP_CODE
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config DUMP_CODE
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bool "Show disassembly of nearby code in register dumps"
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bool "Show disassembly of nearby code in register dumps"
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depends on DEBUG_KERNEL && SUPERH32
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depends on DEBUG_KERNEL
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default y if DEBUG_BUGVERBOSE
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default y if DEBUG_BUGVERBOSE
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default n
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default n
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help
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help
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@@ -59,7 +58,6 @@ config DUMP_CODE
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config DWARF_UNWINDER
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config DWARF_UNWINDER
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bool "Enable the DWARF unwinder for stacktraces"
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bool "Enable the DWARF unwinder for stacktraces"
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select FRAME_POINTER
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select FRAME_POINTER
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depends on SUPERH32
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default n
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default n
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help
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help
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Enabling this option will make stacktraces more accurate, at
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Enabling this option will make stacktraces more accurate, at
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@@ -77,11 +75,6 @@ config SH_NO_BSS_INIT
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For all other cases, say N. If this option seems perplexing, or
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For all other cases, say N. If this option seems perplexing, or
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you aren't sure, say N.
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you aren't sure, say N.
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config SH64_SR_WATCH
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bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
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depends on SUPERH64
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config MCOUNT
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config MCOUNT
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def_bool y
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def_bool y
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depends on SUPERH32
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depends on STACK_DEBUG || FUNCTION_TRACER
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depends on STACK_DEBUG || FUNCTION_TRACER
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+7
-22
@@ -11,7 +11,7 @@
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#
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#
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ifneq ($(SUBARCH),$(ARCH))
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ifneq ($(SUBARCH),$(ARCH))
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ifeq ($(CROSS_COMPILE),)
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ifeq ($(CROSS_COMPILE),)
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CROSS_COMPILE := $(call cc-cross-prefix, $(UTS_MACHINE)-linux- $(UTS_MACHINE)-linux-gnu- $(UTS_MACHINE)-unknown-linux-gnu-)
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CROSS_COMPILE := $(call cc-cross-prefix, sh-linux- sh-linux-gnu- sh-unknown-linux-gnu-)
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endif
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endif
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endif
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endif
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@@ -29,12 +29,9 @@ isa-$(CONFIG_CPU_SH3) := sh3
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isa-$(CONFIG_CPU_SH4) := sh4
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isa-$(CONFIG_CPU_SH4) := sh4
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isa-$(CONFIG_CPU_SH4A) := sh4a
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isa-$(CONFIG_CPU_SH4A) := sh4a
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isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
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isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
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isa-$(CONFIG_CPU_SH5) := shmedia
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ifeq ($(CONFIG_SUPERH32),y)
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isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
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isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
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isa-y := $(isa-y)-up
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isa-y := $(isa-y)-up
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endif
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cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
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cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
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cflags-$(CONFIG_CPU_J2) += $(call cc-option,-mj2,)
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cflags-$(CONFIG_CPU_J2) += $(call cc-option,-mj2,)
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@@ -47,7 +44,6 @@ cflags-$(CONFIG_CPU_SH4) := $(call cc-option,-m4,) \
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cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \
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cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \
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$(call cc-option,-m4a-nofpu,)
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$(call cc-option,-m4a-nofpu,)
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cflags-$(CONFIG_CPU_SH4AL_DSP) += $(call cc-option,-m4al,)
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cflags-$(CONFIG_CPU_SH4AL_DSP) += $(call cc-option,-m4al,)
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cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,)
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ifeq ($(cflags-y),)
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ifeq ($(cflags-y),)
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#
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#
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@@ -88,7 +84,7 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
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-R .stab -R .stabstr -S
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-R .stab -R .stabstr -S
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# Give the various platforms the opportunity to set default image types
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# Give the various platforms the opportunity to set default image types
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defaultimage-$(CONFIG_SUPERH32) := zImage
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defaultimage-y := zImage
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defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
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defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
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defaultimage-$(CONFIG_SH_RSK) := uImage
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defaultimage-$(CONFIG_SH_RSK) := uImage
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defaultimage-$(CONFIG_SH_URQUELL) := uImage
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defaultimage-$(CONFIG_SH_URQUELL) := uImage
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@@ -107,31 +103,22 @@ KBUILD_IMAGE := $(boot)/$(defaultimage-y)
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# Choosing incompatible machines durings configuration will result in
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# Choosing incompatible machines durings configuration will result in
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# error messages during linking.
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# error messages during linking.
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#
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#
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ifdef CONFIG_SUPERH32
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UTS_MACHINE := sh
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UTS_MACHINE := sh
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BITS := 32
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LDFLAGS_vmlinux += -e _stext
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LDFLAGS_vmlinux += -e _stext
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else
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UTS_MACHINE := sh64
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BITS := 64
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LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \
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--defsym phys_stext_shmedia=phys_stext+1 \
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-e phys_stext_shmedia
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endif
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ifdef CONFIG_CPU_LITTLE_ENDIAN
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ifdef CONFIG_CPU_LITTLE_ENDIAN
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ld-bfd := elf32-$(UTS_MACHINE)-linux
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ld-bfd := elf32-sh-linux
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LDFLAGS_vmlinux += --defsym jiffies=jiffies_64 --oformat $(ld-bfd)
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LDFLAGS_vmlinux += --defsym jiffies=jiffies_64 --oformat $(ld-bfd)
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KBUILD_LDFLAGS += -EL
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KBUILD_LDFLAGS += -EL
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else
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else
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ld-bfd := elf32-$(UTS_MACHINE)big-linux
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ld-bfd := elf32-shbig-linux
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LDFLAGS_vmlinux += --defsym jiffies=jiffies_64+4 --oformat $(ld-bfd)
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LDFLAGS_vmlinux += --defsym jiffies=jiffies_64+4 --oformat $(ld-bfd)
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KBUILD_LDFLAGS += -EB
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KBUILD_LDFLAGS += -EB
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endif
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endif
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export ld-bfd BITS
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export ld-bfd
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head-y := arch/sh/kernel/head_$(BITS).o
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head-y := arch/sh/kernel/head_32.o
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core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
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core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
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core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
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core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
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@@ -185,7 +172,6 @@ cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2
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cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3
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cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3
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cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a
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cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a
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cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4
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cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4
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cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5
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cpuincdir-y += cpu-common # Must be last
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cpuincdir-y += cpu-common # Must be last
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drivers-y += arch/sh/drivers/
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drivers-y += arch/sh/drivers/
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@@ -206,8 +192,7 @@ ifeq ($(CONFIG_DWARF_UNWINDER),y)
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KBUILD_CFLAGS += -fasynchronous-unwind-tables
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KBUILD_CFLAGS += -fasynchronous-unwind-tables
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endif
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endif
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libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y)
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libs-y := arch/sh/lib/ $(libs-y)
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libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y)
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BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.xz uImage.lzo \
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BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.xz uImage.lzo \
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uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \
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uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \
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@@ -8,9 +8,9 @@
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targets := vmlinux vmlinux.bin vmlinux.bin.gz \
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targets := vmlinux vmlinux.bin vmlinux.bin.gz \
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vmlinux.bin.bz2 vmlinux.bin.lzma \
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vmlinux.bin.bz2 vmlinux.bin.lzma \
|
||||||
vmlinux.bin.xz vmlinux.bin.lzo \
|
vmlinux.bin.xz vmlinux.bin.lzo \
|
||||||
head_$(BITS).o misc.o piggy.o
|
head_32.o misc.o piggy.o
|
||||||
|
|
||||||
OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o
|
OBJECTS = $(obj)/head_32.o $(obj)/misc.o $(obj)/cache.o
|
||||||
|
|
||||||
GCOV_PROFILE := n
|
GCOV_PROFILE := n
|
||||||
|
|
||||||
@@ -39,15 +39,11 @@ LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(IMAGE_OFFSET) -e startup \
|
|||||||
#
|
#
|
||||||
# Pull in the necessary libgcc bits from the in-kernel implementation.
|
# Pull in the necessary libgcc bits from the in-kernel implementation.
|
||||||
#
|
#
|
||||||
lib1funcs-$(CONFIG_SUPERH32) := ashiftrt.S ashldi3.c ashrsi3.S ashlsi3.S \
|
lib1funcs-y := ashiftrt.S ashldi3.c ashrsi3.S ashlsi3.S lshrsi3.S
|
||||||
lshrsi3.S
|
lib1funcs-obj := \
|
||||||
lib1funcs-obj := \
|
|
||||||
$(addsuffix .o, $(basename $(addprefix $(obj)/, $(lib1funcs-y))))
|
$(addsuffix .o, $(basename $(addprefix $(obj)/, $(lib1funcs-y))))
|
||||||
|
|
||||||
lib1funcs-dir := $(srctree)/arch/$(SRCARCH)/lib
|
lib1funcs-dir := $(srctree)/arch/$(SRCARCH)/lib
|
||||||
ifeq ($(BITS),64)
|
|
||||||
lib1funcs-dir := $(addsuffix $(BITS), $(lib1funcs-dir))
|
|
||||||
endif
|
|
||||||
|
|
||||||
KBUILD_CFLAGS += -I$(lib1funcs-dir) -DDISABLE_BRANCH_PROFILING
|
KBUILD_CFLAGS += -I$(lib1funcs-dir) -DDISABLE_BRANCH_PROFILING
|
||||||
|
|
||||||
|
|||||||
@@ -116,11 +116,7 @@ void ftrace_stub(void)
|
|||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SUPERH64
|
|
||||||
#define stackalign 8
|
|
||||||
#else
|
|
||||||
#define stackalign 4
|
#define stackalign 4
|
||||||
#endif
|
|
||||||
|
|
||||||
#define STACK_SIZE (4096)
|
#define STACK_SIZE (4096)
|
||||||
long __attribute__ ((aligned(stackalign))) user_stack[STACK_SIZE];
|
long __attribute__ ((aligned(stackalign))) user_stack[STACK_SIZE];
|
||||||
@@ -130,13 +126,9 @@ void decompress_kernel(void)
|
|||||||
{
|
{
|
||||||
unsigned long output_addr;
|
unsigned long output_addr;
|
||||||
|
|
||||||
#ifdef CONFIG_SUPERH64
|
|
||||||
output_addr = (CONFIG_MEMORY_START + 0x2000);
|
|
||||||
#else
|
|
||||||
output_addr = __pa((unsigned long)&_text+PAGE_SIZE);
|
output_addr = __pa((unsigned long)&_text+PAGE_SIZE);
|
||||||
#if defined(CONFIG_29BIT)
|
#if defined(CONFIG_29BIT)
|
||||||
output_addr |= P2SEG;
|
output_addr |= P2SEG;
|
||||||
#endif
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
output = (unsigned char *)output_addr;
|
output = (unsigned char *)output_addr;
|
||||||
|
|||||||
@@ -10,7 +10,6 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
|
|||||||
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
|
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
|
||||||
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
|
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
|
||||||
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += pcie-sh7786.o ops-sh7786.o
|
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += pcie-sh7786.o ops-sh7786.o
|
||||||
obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
|
|
||||||
|
|
||||||
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
|
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
|
||||||
pci-dreamcast.o
|
pci-dreamcast.o
|
||||||
|
|||||||
@@ -1,65 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Support functions for the SH5 PCI hardware.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
|
||||||
* Copyright (C) 2003, 2004 Paul Mundt
|
|
||||||
* Copyright (C) 2004 Richard Curnow
|
|
||||||
*/
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/rwsem.h>
|
|
||||||
#include <linux/smp.h>
|
|
||||||
#include <linux/interrupt.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/errno.h>
|
|
||||||
#include <linux/pci.h>
|
|
||||||
#include <linux/delay.h>
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/irq.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include "pci-sh5.h"
|
|
||||||
|
|
||||||
static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
|
||||||
int size, u32 *val)
|
|
||||||
{
|
|
||||||
SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
|
|
||||||
|
|
||||||
switch (size) {
|
|
||||||
case 1:
|
|
||||||
*val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3));
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
*val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2));
|
|
||||||
break;
|
|
||||||
case 4:
|
|
||||||
*val = SH5PCI_READ(PDR);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return PCIBIOS_SUCCESSFUL;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|
||||||
int size, u32 val)
|
|
||||||
{
|
|
||||||
SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
|
|
||||||
|
|
||||||
switch (size) {
|
|
||||||
case 1:
|
|
||||||
SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
|
|
||||||
break;
|
|
||||||
case 4:
|
|
||||||
SH5PCI_WRITE(PDR, val);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return PCIBIOS_SUCCESSFUL;
|
|
||||||
}
|
|
||||||
|
|
||||||
struct pci_ops sh5_pci_ops = {
|
|
||||||
.read = sh5pci_read,
|
|
||||||
.write = sh5pci_write,
|
|
||||||
};
|
|
||||||
@@ -1,217 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
|
||||||
* Copyright (C) 2003, 2004 Paul Mundt
|
|
||||||
* Copyright (C) 2004 Richard Curnow
|
|
||||||
*
|
|
||||||
* Support functions for the SH5 PCI hardware.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/rwsem.h>
|
|
||||||
#include <linux/smp.h>
|
|
||||||
#include <linux/interrupt.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/errno.h>
|
|
||||||
#include <linux/pci.h>
|
|
||||||
#include <linux/delay.h>
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/irq.h>
|
|
||||||
#include <cpu/irq.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include "pci-sh5.h"
|
|
||||||
|
|
||||||
unsigned long pcicr_virt;
|
|
||||||
unsigned long PCI_IO_AREA;
|
|
||||||
|
|
||||||
/* Rounds a number UP to the nearest power of two. Used for
|
|
||||||
* sizing the PCI window.
|
|
||||||
*/
|
|
||||||
static u32 __init r2p2(u32 num)
|
|
||||||
{
|
|
||||||
int i = 31;
|
|
||||||
u32 tmp = num;
|
|
||||||
|
|
||||||
if (num == 0)
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
do {
|
|
||||||
if (tmp & (1 << 31))
|
|
||||||
break;
|
|
||||||
i--;
|
|
||||||
tmp <<= 1;
|
|
||||||
} while (i >= 0);
|
|
||||||
|
|
||||||
tmp = 1 << i;
|
|
||||||
/* If the original number isn't a power of 2, round it up */
|
|
||||||
if (tmp != num)
|
|
||||||
tmp <<= 1;
|
|
||||||
|
|
||||||
return tmp;
|
|
||||||
}
|
|
||||||
|
|
||||||
static irqreturn_t pcish5_err_irq(int irq, void *dev_id)
|
|
||||||
{
|
|
||||||
struct pt_regs *regs = get_irq_regs();
|
|
||||||
unsigned pci_int, pci_air, pci_cir, pci_aint;
|
|
||||||
|
|
||||||
pci_int = SH5PCI_READ(INT);
|
|
||||||
pci_cir = SH5PCI_READ(CIR);
|
|
||||||
pci_air = SH5PCI_READ(AIR);
|
|
||||||
|
|
||||||
if (pci_int) {
|
|
||||||
printk("PCI INTERRUPT (at %08llx)!\n", regs->pc);
|
|
||||||
printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
|
|
||||||
printk("PCI AIR -> 0x%x\n", pci_air);
|
|
||||||
printk("PCI CIR -> 0x%x\n", pci_cir);
|
|
||||||
SH5PCI_WRITE(INT, ~0);
|
|
||||||
}
|
|
||||||
|
|
||||||
pci_aint = SH5PCI_READ(AINT);
|
|
||||||
if (pci_aint) {
|
|
||||||
printk("PCI ARB INTERRUPT!\n");
|
|
||||||
printk("PCI AINT -> 0x%x\n", pci_aint);
|
|
||||||
printk("PCI AIR -> 0x%x\n", pci_air);
|
|
||||||
printk("PCI CIR -> 0x%x\n", pci_cir);
|
|
||||||
SH5PCI_WRITE(AINT, ~0);
|
|
||||||
}
|
|
||||||
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
}
|
|
||||||
|
|
||||||
static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
|
|
||||||
{
|
|
||||||
printk("SERR IRQ\n");
|
|
||||||
|
|
||||||
return IRQ_NONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct resource sh5_pci_resources[2];
|
|
||||||
|
|
||||||
static struct pci_channel sh5pci_controller = {
|
|
||||||
.pci_ops = &sh5_pci_ops,
|
|
||||||
.resources = sh5_pci_resources,
|
|
||||||
.nr_resources = ARRAY_SIZE(sh5_pci_resources),
|
|
||||||
.mem_offset = 0x00000000,
|
|
||||||
.io_offset = 0x00000000,
|
|
||||||
};
|
|
||||||
|
|
||||||
static int __init sh5pci_init(void)
|
|
||||||
{
|
|
||||||
unsigned long memStart = __pa(memory_start);
|
|
||||||
unsigned long memSize = __pa(memory_end) - memStart;
|
|
||||||
u32 lsr0;
|
|
||||||
u32 uval;
|
|
||||||
|
|
||||||
if (request_irq(IRQ_ERR, pcish5_err_irq,
|
|
||||||
0, "PCI Error",NULL) < 0) {
|
|
||||||
printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (request_irq(IRQ_SERR, pcish5_serr_irq,
|
|
||||||
0, "PCI SERR interrupt", NULL) < 0) {
|
|
||||||
printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
pcicr_virt = (unsigned long)ioremap(SH5PCI_ICR_BASE, 1024);
|
|
||||||
if (!pcicr_virt) {
|
|
||||||
panic("Unable to remap PCICR\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
PCI_IO_AREA = (unsigned long)ioremap(SH5PCI_IO_BASE, 0x10000);
|
|
||||||
if (!PCI_IO_AREA) {
|
|
||||||
panic("Unable to remap PCIIO\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Clear snoop registers */
|
|
||||||
SH5PCI_WRITE(CSCR0, 0);
|
|
||||||
SH5PCI_WRITE(CSCR1, 0);
|
|
||||||
|
|
||||||
/* Switch off interrupts */
|
|
||||||
SH5PCI_WRITE(INTM, 0);
|
|
||||||
SH5PCI_WRITE(AINTM, 0);
|
|
||||||
SH5PCI_WRITE(PINTM, 0);
|
|
||||||
|
|
||||||
/* Set bus active, take it out of reset */
|
|
||||||
uval = SH5PCI_READ(CR);
|
|
||||||
|
|
||||||
/* Set command Register */
|
|
||||||
SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE |
|
|
||||||
CR_PFCS | CR_BMAM);
|
|
||||||
|
|
||||||
uval=SH5PCI_READ(CR);
|
|
||||||
|
|
||||||
/* Allow it to be a master */
|
|
||||||
/* NB - WE DISABLE I/O ACCESS to stop overlap */
|
|
||||||
/* set WAIT bit to enable stepping, an attempt to improve stability */
|
|
||||||
SH5PCI_WRITE_SHORT(CSR_CMD,
|
|
||||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
|
||||||
PCI_COMMAND_WAIT);
|
|
||||||
|
|
||||||
/*
|
|
||||||
** Set translation mapping memory in order to convert the address
|
|
||||||
** used for the main bus, to the PCI internal address.
|
|
||||||
*/
|
|
||||||
SH5PCI_WRITE(MBR,0x40000000);
|
|
||||||
|
|
||||||
/* Always set the max size 512M */
|
|
||||||
SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024));
|
|
||||||
|
|
||||||
/*
|
|
||||||
** I/O addresses are mapped at internal PCI specific address
|
|
||||||
** as is described into the configuration bridge table.
|
|
||||||
** These are changed to 0, to allow cards that have legacy
|
|
||||||
** io such as vga to function correctly. We set the SH5 IOBAR to
|
|
||||||
** 256K, which is a bit big as we can only have 64K of address space
|
|
||||||
*/
|
|
||||||
|
|
||||||
SH5PCI_WRITE(IOBR,0x0);
|
|
||||||
|
|
||||||
/* Set up a 256K window. Totally pointless waste of address space */
|
|
||||||
SH5PCI_WRITE(IOBMR,0);
|
|
||||||
|
|
||||||
/* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec.
|
|
||||||
* Ideally, we would want to map the I/O region somewhere, but it
|
|
||||||
* is so big this is not that easy!
|
|
||||||
*/
|
|
||||||
SH5PCI_WRITE(CSR_IBAR0,~0);
|
|
||||||
/* Set memory size value */
|
|
||||||
memSize = memory_end - memory_start;
|
|
||||||
|
|
||||||
/* Now we set up the mbars so the PCI bus can see the memory of
|
|
||||||
* the machine */
|
|
||||||
if (memSize < (1024 * 1024)) {
|
|
||||||
printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n",
|
|
||||||
memSize);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set LSR 0 */
|
|
||||||
lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 :
|
|
||||||
((r2p2(memSize) - 0x100000) | 0x1);
|
|
||||||
SH5PCI_WRITE(LSR0, lsr0);
|
|
||||||
|
|
||||||
/* Set MBAR 0 */
|
|
||||||
SH5PCI_WRITE(CSR_MBAR0, memory_start);
|
|
||||||
SH5PCI_WRITE(LAR0, memory_start);
|
|
||||||
|
|
||||||
SH5PCI_WRITE(CSR_MBAR1,0);
|
|
||||||
SH5PCI_WRITE(LAR1,0);
|
|
||||||
SH5PCI_WRITE(LSR1,0);
|
|
||||||
|
|
||||||
/* Enable the PCI interrupts on the device */
|
|
||||||
SH5PCI_WRITE(INTM, ~0);
|
|
||||||
SH5PCI_WRITE(AINTM, ~0);
|
|
||||||
SH5PCI_WRITE(PINTM, ~0);
|
|
||||||
|
|
||||||
sh5_pci_resources[0].start = PCI_IO_AREA;
|
|
||||||
sh5_pci_resources[0].end = PCI_IO_AREA + 0x10000;
|
|
||||||
|
|
||||||
sh5_pci_resources[1].start = memStart;
|
|
||||||
sh5_pci_resources[1].end = memStart + memSize;
|
|
||||||
|
|
||||||
return register_pci_controller(&sh5pci_controller);
|
|
||||||
}
|
|
||||||
arch_initcall(sh5pci_init);
|
|
||||||
@@ -1,108 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0
|
|
||||||
*
|
|
||||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
|
||||||
*
|
|
||||||
* Definitions for the SH5 PCI hardware.
|
|
||||||
*/
|
|
||||||
#ifndef __PCI_SH5_H
|
|
||||||
#define __PCI_SH5_H
|
|
||||||
|
|
||||||
/* Product ID */
|
|
||||||
#define PCISH5_PID 0x350d
|
|
||||||
|
|
||||||
/* vendor ID */
|
|
||||||
#define PCISH5_VID 0x1054
|
|
||||||
|
|
||||||
/* Configuration types */
|
|
||||||
#define ST_TYPE0 0x00 /* Configuration cycle type 0 */
|
|
||||||
#define ST_TYPE1 0x01 /* Configuration cycle type 1 */
|
|
||||||
|
|
||||||
/* VCR data */
|
|
||||||
#define PCISH5_VCR_STATUS 0x00
|
|
||||||
#define PCISH5_VCR_VERSION 0x08
|
|
||||||
|
|
||||||
/*
|
|
||||||
** ICR register offsets and bits
|
|
||||||
*/
|
|
||||||
#define PCISH5_ICR_CR 0x100 /* PCI control register values */
|
|
||||||
#define CR_PBAM (1<<12)
|
|
||||||
#define CR_PFCS (1<<11)
|
|
||||||
#define CR_FTO (1<<10)
|
|
||||||
#define CR_PFE (1<<9)
|
|
||||||
#define CR_TBS (1<<8)
|
|
||||||
#define CR_SPUE (1<<7)
|
|
||||||
#define CR_BMAM (1<<6)
|
|
||||||
#define CR_HOST (1<<5)
|
|
||||||
#define CR_CLKEN (1<<4)
|
|
||||||
#define CR_SOCS (1<<3)
|
|
||||||
#define CR_IOCS (1<<2)
|
|
||||||
#define CR_RSTCTL (1<<1)
|
|
||||||
#define CR_CFINT (1<<0)
|
|
||||||
#define CR_LOCK_MASK 0xa5000000
|
|
||||||
|
|
||||||
#define PCISH5_ICR_INT 0x114 /* Interrupt registert values */
|
|
||||||
#define INT_MADIM (1<<2)
|
|
||||||
|
|
||||||
#define PCISH5_ICR_LSR0 0X104 /* Local space register values */
|
|
||||||
#define PCISH5_ICR_LSR1 0X108 /* Local space register values */
|
|
||||||
#define PCISH5_ICR_LAR0 0x10c /* Local address register values */
|
|
||||||
#define PCISH5_ICR_LAR1 0x110 /* Local address register values */
|
|
||||||
#define PCISH5_ICR_INTM 0x118 /* Interrupt mask register values */
|
|
||||||
#define PCISH5_ICR_AIR 0x11c /* Interrupt error address information register values */
|
|
||||||
#define PCISH5_ICR_CIR 0x120 /* Interrupt error command information register values */
|
|
||||||
#define PCISH5_ICR_AINT 0x130 /* Interrupt error arbiter interrupt register values */
|
|
||||||
#define PCISH5_ICR_AINTM 0x134 /* Interrupt error arbiter interrupt mask register values */
|
|
||||||
#define PCISH5_ICR_BMIR 0x138 /* Interrupt error info register of bus master values */
|
|
||||||
#define PCISH5_ICR_PAR 0x1c0 /* Pio address register values */
|
|
||||||
#define PCISH5_ICR_MBR 0x1c4 /* Memory space bank register values */
|
|
||||||
#define PCISH5_ICR_IOBR 0x1c8 /* I/O space bank register values */
|
|
||||||
#define PCISH5_ICR_PINT 0x1cc /* power management interrupt register values */
|
|
||||||
#define PCISH5_ICR_PINTM 0x1d0 /* power management interrupt mask register values */
|
|
||||||
#define PCISH5_ICR_MBMR 0x1d8 /* memory space bank mask register values */
|
|
||||||
#define PCISH5_ICR_IOBMR 0x1dc /* I/O space bank mask register values */
|
|
||||||
#define PCISH5_ICR_CSCR0 0x210 /* PCI cache snoop control register 0 */
|
|
||||||
#define PCISH5_ICR_CSCR1 0x214 /* PCI cache snoop control register 1 */
|
|
||||||
#define PCISH5_ICR_PDR 0x220 /* Pio data register values */
|
|
||||||
|
|
||||||
/* These are configs space registers */
|
|
||||||
#define PCISH5_ICR_CSR_VID 0x000 /* Vendor id */
|
|
||||||
#define PCISH5_ICR_CSR_DID 0x002 /* Device id */
|
|
||||||
#define PCISH5_ICR_CSR_CMD 0x004 /* Command register */
|
|
||||||
#define PCISH5_ICR_CSR_STATUS 0x006 /* Stautus */
|
|
||||||
#define PCISH5_ICR_CSR_IBAR0 0x010 /* I/O base address register */
|
|
||||||
#define PCISH5_ICR_CSR_MBAR0 0x014 /* First Memory base address register */
|
|
||||||
#define PCISH5_ICR_CSR_MBAR1 0x018 /* Second Memory base address register */
|
|
||||||
|
|
||||||
/* Base address of registers */
|
|
||||||
#define SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000)
|
|
||||||
#define SH5PCI_IO_BASE (PHYS_PCI_BLOCK + 0x00800000)
|
|
||||||
/* #define SH5PCI_VCR_BASE (P2SEG_PCICB_BLOCK + P2SEG) */
|
|
||||||
|
|
||||||
extern unsigned long pcicr_virt;
|
|
||||||
/* Register selection macro */
|
|
||||||
#define PCISH5_ICR_REG(x) ( pcicr_virt + (PCISH5_ICR_##x))
|
|
||||||
/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
|
|
||||||
|
|
||||||
/* Write I/O functions */
|
|
||||||
#define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
|
|
||||||
#define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
|
|
||||||
#define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
|
|
||||||
|
|
||||||
/* Read I/O functions */
|
|
||||||
#define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg))
|
|
||||||
#define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg))
|
|
||||||
#define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg))
|
|
||||||
|
|
||||||
/* Set PCI config bits */
|
|
||||||
#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
|
|
||||||
|
|
||||||
/* Set PCI command register */
|
|
||||||
#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
|
|
||||||
|
|
||||||
/* Size converters */
|
|
||||||
#define PCISH5_MEM_SIZCONV(x) (((x / 0x40000) - 1) << 18)
|
|
||||||
#define PCISH5_IO_SIZCONV(x) (((x / 0x40000) - 1) << 18)
|
|
||||||
|
|
||||||
extern struct pci_ops sh5_pci_ops;
|
|
||||||
|
|
||||||
#endif /* __PCI_SH5_H */
|
|
||||||
@@ -6,7 +6,7 @@
|
|||||||
#ifndef __ASM_SH_BARRIER_H
|
#ifndef __ASM_SH_BARRIER_H
|
||||||
#define __ASM_SH_BARRIER_H
|
#define __ASM_SH_BARRIER_H
|
||||||
|
|
||||||
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
|
#if defined(CONFIG_CPU_SH4A)
|
||||||
#include <asm/cache_insns.h>
|
#include <asm/cache_insns.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@@ -24,7 +24,7 @@
|
|||||||
* Historically we have only done this type of barrier for the MMUCR, but
|
* Historically we have only done this type of barrier for the MMUCR, but
|
||||||
* it's also necessary for the CCR, so we make it generic here instead.
|
* it's also necessary for the CCR, so we make it generic here instead.
|
||||||
*/
|
*/
|
||||||
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
|
#if defined(CONFIG_CPU_SH4A)
|
||||||
#define mb() __asm__ __volatile__ ("synco": : :"memory")
|
#define mb() __asm__ __volatile__ ("synco": : :"memory")
|
||||||
#define rmb() mb()
|
#define rmb() mb()
|
||||||
#define wmb() mb()
|
#define wmb() mb()
|
||||||
|
|||||||
@@ -26,7 +26,6 @@
|
|||||||
#include <asm-generic/bitops/non-atomic.h>
|
#include <asm-generic/bitops/non-atomic.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SUPERH32
|
|
||||||
static inline unsigned long ffz(unsigned long word)
|
static inline unsigned long ffz(unsigned long word)
|
||||||
{
|
{
|
||||||
unsigned long result;
|
unsigned long result;
|
||||||
@@ -60,31 +59,6 @@ static inline unsigned long __ffs(unsigned long word)
|
|||||||
: "t");
|
: "t");
|
||||||
return result;
|
return result;
|
||||||
}
|
}
|
||||||
#else
|
|
||||||
static inline unsigned long ffz(unsigned long word)
|
|
||||||
{
|
|
||||||
unsigned long result, __d2, __d3;
|
|
||||||
|
|
||||||
__asm__("gettr tr0, %2\n\t"
|
|
||||||
"pta $+32, tr0\n\t"
|
|
||||||
"andi %1, 1, %3\n\t"
|
|
||||||
"beq %3, r63, tr0\n\t"
|
|
||||||
"pta $+4, tr0\n"
|
|
||||||
"0:\n\t"
|
|
||||||
"shlri.l %1, 1, %1\n\t"
|
|
||||||
"addi %0, 1, %0\n\t"
|
|
||||||
"andi %1, 1, %3\n\t"
|
|
||||||
"beqi %3, 1, tr0\n"
|
|
||||||
"1:\n\t"
|
|
||||||
"ptabs %2, tr0\n\t"
|
|
||||||
: "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
|
|
||||||
: "0" (0L), "1" (word));
|
|
||||||
|
|
||||||
return result;
|
|
||||||
}
|
|
||||||
|
|
||||||
#include <asm-generic/bitops/__ffs.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <asm-generic/bitops/find.h>
|
#include <asm-generic/bitops/find.h>
|
||||||
#include <asm-generic/bitops/ffs.h>
|
#include <asm-generic/bitops/ffs.h>
|
||||||
|
|||||||
@@ -1,11 +1,2 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
#ifndef __ASM_SH_BL_BIT_H
|
#include <asm/bl_bit_32.h>
|
||||||
#define __ASM_SH_BL_BIT_H
|
|
||||||
|
|
||||||
#ifdef CONFIG_SUPERH32
|
|
||||||
# include <asm/bl_bit_32.h>
|
|
||||||
#else
|
|
||||||
# include <asm/bl_bit_64.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __ASM_SH_BL_BIT_H */
|
|
||||||
|
|||||||
@@ -1,37 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
|
||||||
* Copyright (C) 2003 Paul Mundt
|
|
||||||
* Copyright (C) 2004 Richard Curnow
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_SH_BL_BIT_64_H
|
|
||||||
#define __ASM_SH_BL_BIT_64_H
|
|
||||||
|
|
||||||
#include <asm/processor.h>
|
|
||||||
|
|
||||||
#define SR_BL_LL 0x0000000010000000LL
|
|
||||||
|
|
||||||
static inline void set_bl_bit(void)
|
|
||||||
{
|
|
||||||
unsigned long long __dummy0, __dummy1 = SR_BL_LL;
|
|
||||||
|
|
||||||
__asm__ __volatile__("getcon " __SR ", %0\n\t"
|
|
||||||
"or %0, %1, %0\n\t"
|
|
||||||
"putcon %0, " __SR "\n\t"
|
|
||||||
: "=&r" (__dummy0)
|
|
||||||
: "r" (__dummy1));
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void clear_bl_bit(void)
|
|
||||||
{
|
|
||||||
unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
|
|
||||||
|
|
||||||
__asm__ __volatile__("getcon " __SR ", %0\n\t"
|
|
||||||
"and %0, %1, %0\n\t"
|
|
||||||
"putcon %0, " __SR "\n\t"
|
|
||||||
: "=&r" (__dummy0)
|
|
||||||
: "r" (__dummy1));
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __ASM_SH_BL_BIT_64_H */
|
|
||||||
@@ -53,10 +53,6 @@ static void __init check_bugs(void)
|
|||||||
*p++ = 's';
|
*p++ = 's';
|
||||||
*p++ = 'p';
|
*p++ = 'p';
|
||||||
break;
|
break;
|
||||||
case CPU_FAMILY_SH5:
|
|
||||||
*p++ = '6';
|
|
||||||
*p++ = '4';
|
|
||||||
break;
|
|
||||||
case CPU_FAMILY_UNKNOWN:
|
case CPU_FAMILY_UNKNOWN:
|
||||||
/*
|
/*
|
||||||
* Specifically use CPU_FAMILY_UNKNOWN rather than
|
* Specifically use CPU_FAMILY_UNKNOWN rather than
|
||||||
|
|||||||
@@ -1,12 +1,2 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
#ifndef __ASM_SH_CACHE_INSNS_H
|
#include <asm/cache_insns_32.h>
|
||||||
#define __ASM_SH_CACHE_INSNS_H
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_SUPERH32
|
|
||||||
# include <asm/cache_insns_32.h>
|
|
||||||
#else
|
|
||||||
# include <asm/cache_insns_64.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __ASM_SH_CACHE_INSNS_H */
|
|
||||||
|
|||||||
@@ -1,20 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
|
||||||
* Copyright (C) 2003 Paul Mundt
|
|
||||||
* Copyright (C) 2004 Richard Curnow
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_SH_CACHE_INSNS_64_H
|
|
||||||
#define __ASM_SH_CACHE_INSNS_64_H
|
|
||||||
|
|
||||||
#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
|
|
||||||
#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
|
|
||||||
#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
|
|
||||||
#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
|
|
||||||
|
|
||||||
static inline reg_size_t register_align(void *val)
|
|
||||||
{
|
|
||||||
return (unsigned long long)(signed long long)(signed long)val;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __ASM_SH_CACHE_INSNS_64_H */
|
|
||||||
@@ -1,6 +1,2 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
#ifdef CONFIG_SUPERH32
|
#include <asm/checksum_32.h>
|
||||||
# include <asm/checksum_32.h>
|
|
||||||
#else
|
|
||||||
# include <asm-generic/checksum.h>
|
|
||||||
#endif
|
|
||||||
|
|||||||
@@ -133,28 +133,6 @@ typedef struct user_fpu_struct elf_fpregset_t;
|
|||||||
|
|
||||||
#define ELF_PLATFORM (utsname()->machine)
|
#define ELF_PLATFORM (utsname()->machine)
|
||||||
|
|
||||||
#ifdef __SH5__
|
|
||||||
#define ELF_PLAT_INIT(_r, load_addr) \
|
|
||||||
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
|
|
||||||
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
|
|
||||||
_r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
|
|
||||||
_r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; _r->regs[15]=0; \
|
|
||||||
_r->regs[16]=0; _r->regs[17]=0; _r->regs[18]=0; _r->regs[19]=0; \
|
|
||||||
_r->regs[20]=0; _r->regs[21]=0; _r->regs[22]=0; _r->regs[23]=0; \
|
|
||||||
_r->regs[24]=0; _r->regs[25]=0; _r->regs[26]=0; _r->regs[27]=0; \
|
|
||||||
_r->regs[28]=0; _r->regs[29]=0; _r->regs[30]=0; _r->regs[31]=0; \
|
|
||||||
_r->regs[32]=0; _r->regs[33]=0; _r->regs[34]=0; _r->regs[35]=0; \
|
|
||||||
_r->regs[36]=0; _r->regs[37]=0; _r->regs[38]=0; _r->regs[39]=0; \
|
|
||||||
_r->regs[40]=0; _r->regs[41]=0; _r->regs[42]=0; _r->regs[43]=0; \
|
|
||||||
_r->regs[44]=0; _r->regs[45]=0; _r->regs[46]=0; _r->regs[47]=0; \
|
|
||||||
_r->regs[48]=0; _r->regs[49]=0; _r->regs[50]=0; _r->regs[51]=0; \
|
|
||||||
_r->regs[52]=0; _r->regs[53]=0; _r->regs[54]=0; _r->regs[55]=0; \
|
|
||||||
_r->regs[56]=0; _r->regs[57]=0; _r->regs[58]=0; _r->regs[59]=0; \
|
|
||||||
_r->regs[60]=0; _r->regs[61]=0; _r->regs[62]=0; \
|
|
||||||
_r->tregs[0]=0; _r->tregs[1]=0; _r->tregs[2]=0; _r->tregs[3]=0; \
|
|
||||||
_r->tregs[4]=0; _r->tregs[5]=0; _r->tregs[6]=0; _r->tregs[7]=0; \
|
|
||||||
_r->sr = SR_FD | SR_MMU; } while (0)
|
|
||||||
#else
|
|
||||||
#define ELF_PLAT_INIT(_r, load_addr) \
|
#define ELF_PLAT_INIT(_r, load_addr) \
|
||||||
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
|
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
|
||||||
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
|
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
|
||||||
@@ -182,7 +160,6 @@ do { \
|
|||||||
_r->regs[14] = 0; \
|
_r->regs[14] = 0; \
|
||||||
_r->sr = SR_FD; \
|
_r->sr = SR_FD; \
|
||||||
} while (0)
|
} while (0)
|
||||||
#endif
|
|
||||||
|
|
||||||
#define SET_PERSONALITY(ex) \
|
#define SET_PERSONALITY(ex) \
|
||||||
set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
|
set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
|
||||||
|
|||||||
@@ -4,8 +4,4 @@
|
|||||||
|
|
||||||
#include <asm-generic/extable.h>
|
#include <asm-generic/extable.h>
|
||||||
|
|
||||||
#if defined(CONFIG_SUPERH64) && defined(CONFIG_MMU)
|
|
||||||
#define ARCH_HAS_SEARCH_EXTABLE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
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Reference in New Issue
Block a user