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https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
pinctrl: sophgo: add support for SG2042 SoC
Add base driver for SG2042 SoC and pin definition. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/20250211051801.470800-7-inochiama@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Inochi Amaoto
committed by
Linus Walleij
Linus Walleij
parent
68ea8c8779
commit
1e67465d3b
@@ -59,3 +59,18 @@ config PINCTRL_SOPHGO_SG2002
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This pin controller allows selecting the mux function for
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each pin. This driver can also be built as a module called
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pinctrl-sg2002.
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config PINCTRL_SOPHGO_SG2042_OPS
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bool
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config PINCTRL_SOPHGO_SG2042
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tristate "Sophgo SG2042 SoC Pinctrl driver"
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depends on ARCH_SOPHGO || COMPILE_TEST
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depends on OF
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select PINCTRL_SOPHGO_COMMON
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select PINCTRL_SOPHGO_SG2042_OPS
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help
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Say Y to select the pinctrl driver for SG2042 SoC.
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This pin controller allows selecting the mux function for
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each pin. This driver can also be built as a module called
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pinctrl-sg2042.
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@@ -3,8 +3,10 @@
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obj-$(CONFIG_PINCTRL_SOPHGO_COMMON) += pinctrl-sophgo.o
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pinctrl-sophgo-objs += pinctrl-sophgo-common.o
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pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_CV18XX_OPS) += pinctrl-cv18xx.o
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pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_SG2042_OPS) += pinctrl-sg2042-ops.o
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obj-$(CONFIG_PINCTRL_SOPHGO_CV1800B) += pinctrl-cv1800b.o
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obj-$(CONFIG_PINCTRL_SOPHGO_CV1812H) += pinctrl-cv1812h.o
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obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o
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obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o
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obj-$(CONFIG_PINCTRL_SOPHGO_SG2042) += pinctrl-sg2042.o
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@@ -0,0 +1,296 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Sophgo sg2042 SoCs pinctrl driver.
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*
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* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include "../pinctrl-utils.h"
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#include "../pinmux.h"
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#include "pinctrl-sg2042.h"
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#define PIN_IO_PULL_ONE_ENABLE BIT(0)
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#define PIN_IO_PULL_DIR_UP (BIT(1) | PIN_IO_PULL_ONE_ENABLE)
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#define PIN_IO_PULL_DIR_DOWN (0 | PIN_IO_PULL_ONE_ENABLE)
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#define PIN_IO_PULL_ONE_MASK GENMASK(1, 0)
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#define PIN_IO_PULL_UP BIT(2)
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#define PIN_IO_PULL_UP_DONW BIT(3)
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#define PIN_IO_PULL_UP_MASK GENMASK(3, 2)
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#define PIN_IO_MUX GENMASK(5, 4)
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#define PIN_IO_DRIVE GENMASK(9, 6)
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#define PIN_IO_SCHMITT_ENABLE BIT(10)
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#define PIN_IO_OUTPUT_ENABLE BIT(11)
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struct sg2042_priv {
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void __iomem *regs;
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};
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static u8 sg2042_dt_get_pin_mux(u32 value)
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{
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return value >> 16;
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}
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static inline u32 sg2042_get_pin_reg(struct sophgo_pinctrl *pctrl,
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const struct sophgo_pin *sp)
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{
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struct sg2042_priv *priv = pctrl->priv_ctrl;
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const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp);
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void __iomem *reg = priv->regs + pin->offset;
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if (sp->flags & PIN_FLAG_WRITE_HIGH)
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return readl(reg) >> 16;
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else
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return readl(reg) & 0xffff;
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}
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static int sg2042_set_pin_reg(struct sophgo_pinctrl *pctrl,
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const struct sophgo_pin *sp,
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u32 value, u32 mask)
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{
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struct sg2042_priv *priv = pctrl->priv_ctrl;
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const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp);
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void __iomem *reg = priv->regs + pin->offset;
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u32 v = readl(reg);
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if (sp->flags & PIN_FLAG_WRITE_HIGH) {
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v &= ~(mask << 16);
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v |= value << 16;
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} else {
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v &= ~mask;
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v |= value;
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}
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writel(v, reg);
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return 0;
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}
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static void sg2042_pctrl_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *seq, unsigned int pin_id)
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{
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struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
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u32 value, mux;
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value = sg2042_get_pin_reg(pctrl, sp);
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mux = FIELD_GET(PIN_IO_MUX, value);
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seq_printf(seq, "mux:%u reg:0x%04x ", mux, value);
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}
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const struct pinctrl_ops sg2042_pctrl_ops = {
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.get_groups_count = pinctrl_generic_get_group_count,
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.get_group_name = pinctrl_generic_get_group_name,
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.get_group_pins = pinctrl_generic_get_group_pins,
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.pin_dbg_show = sg2042_pctrl_dbg_show,
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.dt_node_to_map = sophgo_pctrl_dt_node_to_map,
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.dt_free_map = pinctrl_utils_free_map,
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};
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EXPORT_SYMBOL_GPL(sg2042_pctrl_ops);
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static void sg2042_set_pinmux_config(struct sophgo_pinctrl *pctrl,
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const struct sophgo_pin *sp, u32 config)
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{
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u32 mux = sg2042_dt_get_pin_mux(config);
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if (!(sp->flags & PIN_FLAG_NO_PINMUX))
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sg2042_set_pin_reg(pctrl, sp, mux, PIN_IO_MUX);
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}
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const struct pinmux_ops sg2042_pmx_ops = {
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.get_functions_count = pinmux_generic_get_function_count,
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.get_function_name = pinmux_generic_get_function_name,
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.get_function_groups = pinmux_generic_get_function_groups,
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.set_mux = sophgo_pmx_set_mux,
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.strict = true,
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};
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EXPORT_SYMBOL_GPL(sg2042_pmx_ops);
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static int sg2042_pconf_get(struct pinctrl_dev *pctldev,
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unsigned int pin_id, unsigned long *config)
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{
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struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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int param = pinconf_to_config_param(*config);
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const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
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u32 value;
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u32 arg;
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bool enabled;
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int ret;
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if (!sp)
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return -EINVAL;
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value = sg2042_get_pin_reg(pctrl, sp);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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if (sp->flags & PIN_FLAG_ONLY_ONE_PULL)
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arg = FIELD_GET(PIN_IO_PULL_ONE_ENABLE, value);
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else
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arg = FIELD_GET(PIN_IO_PULL_UP_MASK, value);
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enabled = arg == 0;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
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arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value);
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enabled = arg == PIN_IO_PULL_DIR_DOWN;
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} else {
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enabled = FIELD_GET(PIN_IO_PULL_UP_DONW, value) != 0;
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}
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arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, NULL);
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
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arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value);
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enabled = arg == PIN_IO_PULL_DIR_UP;
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} else {
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enabled = FIELD_GET(PIN_IO_PULL_UP, value) != 0;
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}
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arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, NULL);
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break;
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case PIN_CONFIG_DRIVE_STRENGTH_UA:
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enabled = FIELD_GET(PIN_IO_OUTPUT_ENABLE, value) != 0;
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arg = FIELD_GET(PIN_IO_DRIVE, value);
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ret = sophgo_pinctrl_reg2oc(pctrl, sp, NULL, arg);
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if (ret < 0)
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return ret;
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arg = ret;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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arg = FIELD_GET(PIN_IO_SCHMITT_ENABLE, value);
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enabled = arg != 0;
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return enabled ? 0 : -EINVAL;
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}
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static int sg2042_pinconf_compute_config(struct sophgo_pinctrl *pctrl,
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const struct sophgo_pin *sp,
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unsigned long *configs,
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unsigned int num_configs,
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u32 *value, u32 *mask)
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{
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int i;
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u16 v = 0, m = 0;
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int ret;
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if (!sp)
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return -EINVAL;
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for (i = 0; i < num_configs; i++) {
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int param = pinconf_to_config_param(configs[i]);
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u32 arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
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v &= ~PIN_IO_PULL_ONE_ENABLE;
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m |= PIN_IO_PULL_ONE_ENABLE;
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} else {
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v &= ~PIN_IO_PULL_UP_MASK;
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m |= PIN_IO_PULL_UP_MASK;
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}
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
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v &= ~PIN_IO_PULL_ONE_MASK;
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v |= PIN_IO_PULL_DIR_DOWN;
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m |= PIN_IO_PULL_ONE_MASK;
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} else {
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v |= PIN_IO_PULL_UP_DONW;
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m |= PIN_IO_PULL_UP_DONW;
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}
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
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v &= ~PIN_IO_PULL_ONE_MASK;
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v |= PIN_IO_PULL_DIR_UP;
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m |= PIN_IO_PULL_ONE_MASK;
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} else {
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v |= PIN_IO_PULL_UP;
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m |= PIN_IO_PULL_UP;
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}
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break;
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case PIN_CONFIG_DRIVE_STRENGTH_UA:
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v &= ~(PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE);
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if (arg != 0) {
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ret = sophgo_pinctrl_oc2reg(pctrl, sp, NULL, arg);
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if (ret < 0)
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return ret;
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if (!(sp->flags & PIN_FLAG_NO_OEX_EN))
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v |= PIN_IO_OUTPUT_ENABLE;
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v |= FIELD_PREP(PIN_IO_DRIVE, ret);
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}
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m |= PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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v |= PIN_IO_SCHMITT_ENABLE;
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m |= PIN_IO_SCHMITT_ENABLE;
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break;
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default:
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return -ENOTSUPP;
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}
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}
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*value = v;
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*mask = m;
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return 0;
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}
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const struct pinconf_ops sg2042_pconf_ops = {
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.pin_config_get = sg2042_pconf_get,
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.pin_config_set = sophgo_pconf_set,
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.pin_config_group_set = sophgo_pconf_group_set,
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.is_generic = true,
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};
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EXPORT_SYMBOL_GPL(sg2042_pconf_ops);
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static int sophgo_pinctrl_init(struct platform_device *pdev,
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struct sophgo_pinctrl *pctrl)
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{
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struct sg2042_priv *priv;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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pctrl->priv_ctrl = priv;
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return 0;
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}
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const struct sophgo_cfg_ops sg2042_cfg_ops = {
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.pctrl_init = sophgo_pinctrl_init,
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.compute_pinconf_config = sg2042_pinconf_compute_config,
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.set_pinconf_config = sg2042_set_pin_reg,
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.set_pinmux_config = sg2042_set_pinmux_config,
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};
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EXPORT_SYMBOL_GPL(sg2042_cfg_ops);
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,49 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
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*/
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#ifndef _PINCTRL_SOPHGO_SG2042_H
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#define _PINCTRL_SOPHGO_SG2042_H
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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#include "pinctrl-sophgo.h"
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#define PIN_FLAG_DEFAULT 0
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#define PIN_FLAG_WRITE_HIGH BIT(0)
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#define PIN_FLAG_ONLY_ONE_PULL BIT(1)
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#define PIN_FLAG_NO_PINMUX BIT(2)
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#define PIN_FLAG_NO_OEX_EN BIT(3)
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#define PIN_FLAG_IS_ETH BIT(4)
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struct sg2042_pin {
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struct sophgo_pin pin;
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u16 offset;
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};
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#define sophgo_to_sg2042_pin(_pin) \
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container_of((_pin), struct sg2042_pin, pin)
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extern const struct pinctrl_ops sg2042_pctrl_ops;
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extern const struct pinmux_ops sg2042_pmx_ops;
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extern const struct pinconf_ops sg2042_pconf_ops;
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extern const struct sophgo_cfg_ops sg2042_cfg_ops;
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#define SG2042_GENERAL_PIN(_id, _offset, _flag) \
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{ \
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.pin = { \
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.id = (_id), \
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.flags = (_flag), \
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}, \
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.offset = (_offset), \
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}
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#endif
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