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crypto: qat - add qat_6xxx driver
Add a new driver, qat_6xxx, to support QAT GEN6 devices. QAT GEN6 devices are a follow-on generation of GEN4 devices and differently from the previous generation, they can support all three services (symmetric, asymmetric, and data compression) concurrently. In order to have the qat_6xxx driver to reuse some of the GEN4 logic, a new abstraction layer has been introduced to bridge the two implementations. This allows to avoid code duplication and to keep the qat_6xxx driver isolated from the GEN4 logic. This approach has been used for the PF to VF logic and the HW CSR access logic. Signed-off-by: Laurent M Coquerel <laurent.m.coquerel@intel.com> Co-developed-by: George Abraham P <george.abraham.p@intel.com> Signed-off-by: George Abraham P <george.abraham.p@intel.com> Co-developed-by: Karthikeyan Gopal <karthikeyan.gopal@intel.com> Signed-off-by: Karthikeyan Gopal <karthikeyan.gopal@intel.com> Co-developed-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Laurent M Coquerel
committed by
Herbert Xu
Herbert Xu
parent
942028bc2f
commit
17fd7514ae
@@ -70,6 +70,18 @@ config CRYPTO_DEV_QAT_420XX
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To compile this as a module, choose M here: the module
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will be called qat_420xx.
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config CRYPTO_DEV_QAT_6XXX
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tristate "Support for Intel(R) QuickAssist Technology QAT_6XXX"
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depends on (X86 || COMPILE_TEST)
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depends on PCI
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select CRYPTO_DEV_QAT
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help
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Support for Intel(R) QuickAssist Technology QAT_6xxx
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for accelerating crypto and compression workloads.
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To compile this as a module, choose M here: the module
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will be called qat_6xxx.
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config CRYPTO_DEV_QAT_DH895xCCVF
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tristate "Support for Intel(R) DH895xCC Virtual Function"
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depends on PCI && (!CPU_BIG_ENDIAN || COMPILE_TEST)
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@@ -6,6 +6,7 @@ obj-$(CONFIG_CRYPTO_DEV_QAT_C3XXX) += qat_c3xxx/
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obj-$(CONFIG_CRYPTO_DEV_QAT_C62X) += qat_c62x/
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obj-$(CONFIG_CRYPTO_DEV_QAT_4XXX) += qat_4xxx/
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obj-$(CONFIG_CRYPTO_DEV_QAT_420XX) += qat_420xx/
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obj-$(CONFIG_CRYPTO_DEV_QAT_6XXX) += qat_6xxx/
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obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCCVF) += qat_dh895xccvf/
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obj-$(CONFIG_CRYPTO_DEV_QAT_C3XXXVF) += qat_c3xxxvf/
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obj-$(CONFIG_CRYPTO_DEV_QAT_C62XVF) += qat_c62xvf/
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@@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CRYPTO_DEV_QAT_6XXX) += qat_6xxx.o
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qat_6xxx-y := adf_drv.o adf_6xxx_hw_data.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,148 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2025 Intel Corporation */
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#ifndef ADF_6XXX_HW_DATA_H_
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#define ADF_6XXX_HW_DATA_H_
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#include <linux/bits.h>
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#include <linux/time.h>
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#include <linux/units.h>
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#include "adf_accel_devices.h"
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#include "adf_cfg_common.h"
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#include "adf_dc.h"
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/* PCIe configuration space */
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#define ADF_GEN6_BAR_MASK (BIT(0) | BIT(2) | BIT(4))
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#define ADF_GEN6_SRAM_BAR 0
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#define ADF_GEN6_PMISC_BAR 1
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#define ADF_GEN6_ETR_BAR 2
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#define ADF_6XXX_MAX_ACCELENGINES 9
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/* Clocks frequency */
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#define ADF_GEN6_COUNTER_FREQ (100 * HZ_PER_MHZ)
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/* Physical function fuses */
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#define ADF_GEN6_FUSECTL0_OFFSET 0x2C8
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#define ADF_GEN6_FUSECTL1_OFFSET 0x2CC
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#define ADF_GEN6_FUSECTL4_OFFSET 0x2D8
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/* Accelerators */
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#define ADF_GEN6_ACCELERATORS_MASK 0x1
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#define ADF_GEN6_MAX_ACCELERATORS 1
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/* MSI-X interrupt */
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#define ADF_GEN6_SMIAPF_RP_X0_MASK_OFFSET 0x41A040
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#define ADF_GEN6_SMIAPF_RP_X1_MASK_OFFSET 0x41A044
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#define ADF_GEN6_SMIAPF_MASK_OFFSET 0x41A084
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#define ADF_GEN6_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i) * 4))
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/* Bank and ring configuration */
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#define ADF_GEN6_NUM_RINGS_PER_BANK 2
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#define ADF_GEN6_NUM_BANKS_PER_VF 4
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#define ADF_GEN6_ETR_MAX_BANKS 64
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#define ADF_GEN6_RX_RINGS_OFFSET 1
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#define ADF_GEN6_TX_RINGS_MASK 0x1
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/* Arbiter configuration */
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#define ADF_GEN6_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
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#define ADF_GEN6_ARB_OFFSET 0x000
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#define ADF_GEN6_ARB_WRK_2_SER_MAP_OFFSET 0x400
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/* Admin interface configuration */
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#define ADF_GEN6_ADMINMSGUR_OFFSET 0x500574
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#define ADF_GEN6_ADMINMSGLR_OFFSET 0x500578
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#define ADF_GEN6_MAILBOX_BASE_OFFSET 0x600970
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/*
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* Watchdog timers
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* Timeout is in cycles. Clock speed may vary across products but this
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* value should be a few milli-seconds.
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*/
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#define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL
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#define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000ULL
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#define ADF_SSMWDTATHL_OFFSET 0x5208
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#define ADF_SSMWDTATHH_OFFSET 0x520C
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#define ADF_SSMWDTCNVL_OFFSET 0x5408
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#define ADF_SSMWDTCNVH_OFFSET 0x540C
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#define ADF_SSMWDTUCSL_OFFSET 0x5808
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#define ADF_SSMWDTUCSH_OFFSET 0x580C
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#define ADF_SSMWDTDCPRL_OFFSET 0x5A08
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#define ADF_SSMWDTDCPRH_OFFSET 0x5A0C
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#define ADF_SSMWDTPKEL_OFFSET 0x5E08
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#define ADF_SSMWDTPKEH_OFFSET 0x5E0C
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/* Ring reset */
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#define ADF_RPRESET_POLL_TIMEOUT_US (5 * USEC_PER_SEC)
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#define ADF_RPRESET_POLL_DELAY_US 20
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#define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0)
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#define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + (bank) * 8)
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#define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0)
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#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)
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/* Controls and sets up the corresponding ring mode of operation */
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#define ADF_GEN6_CSR_RINGMODECTL(bank) (0x9000 + (bank) * 4)
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/* Specifies the traffic class to use for the transactions to/from the ring */
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#define ADF_GEN6_RINGMODECTL_TC_MASK GENMASK(18, 16)
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#define ADF_GEN6_RINGMODECTL_TC_DEFAULT 0x7
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/* Specifies usage of tc for the transactions to/from this ring */
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#define ADF_GEN6_RINGMODECTL_TC_EN_MASK GENMASK(20, 19)
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/*
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* Use the value programmed in the tc field for request descriptor
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* and metadata read transactions
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*/
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#define ADF_GEN6_RINGMODECTL_TC_EN_OP1 0x1
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/* VC0 Resource Control Register */
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#define ADF_GEN6_PVC0CTL_OFFSET 0x204
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#define ADF_GEN6_PVC0CTL_TCVCMAP_OFFSET 1
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#define ADF_GEN6_PVC0CTL_TCVCMAP_MASK GENMASK(7, 1)
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#define ADF_GEN6_PVC0CTL_TCVCMAP_DEFAULT 0x7F
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/* VC1 Resource Control Register */
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#define ADF_GEN6_PVC1CTL_OFFSET 0x210
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#define ADF_GEN6_PVC1CTL_TCVCMAP_OFFSET 1
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#define ADF_GEN6_PVC1CTL_TCVCMAP_MASK GENMASK(7, 1)
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#define ADF_GEN6_PVC1CTL_TCVCMAP_DEFAULT 0x40
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#define ADF_GEN6_PVC1CTL_VCEN_OFFSET 31
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#define ADF_GEN6_PVC1CTL_VCEN_MASK BIT(31)
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/* RW bit: 0x1 - enables a Virtual Channel, 0x0 - disables */
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#define ADF_GEN6_PVC1CTL_VCEN_ON 0x1
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/* Error source mask registers */
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#define ADF_GEN6_ERRMSK0 0x41A210
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#define ADF_GEN6_ERRMSK1 0x41A214
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#define ADF_GEN6_ERRMSK2 0x41A218
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#define ADF_GEN6_ERRMSK3 0x41A21C
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#define ADF_GEN6_VFLNOTIFY BIT(7)
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/* Number of heartbeat counter pairs */
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#define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE
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/* Physical function fuses */
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#define ADF_6XXX_ACCELENGINES_MASK GENMASK(8, 0)
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#define ADF_6XXX_ADMIN_AE_MASK GENMASK(8, 8)
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/* Firmware binaries */
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#define ADF_6XXX_FW "qat_6xxx.bin"
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#define ADF_6XXX_MMP "qat_6xxx_mmp.bin"
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#define ADF_6XXX_CY_OBJ "qat_6xxx_cy.bin"
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#define ADF_6XXX_DC_OBJ "qat_6xxx_dc.bin"
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#define ADF_6XXX_ADMIN_OBJ "qat_6xxx_admin.bin"
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enum icp_qat_gen6_slice_mask {
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ICP_ACCEL_GEN6_MASK_UCS_SLICE = BIT(0),
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ICP_ACCEL_GEN6_MASK_AUTH_SLICE = BIT(1),
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ICP_ACCEL_GEN6_MASK_PKE_SLICE = BIT(2),
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ICP_ACCEL_GEN6_MASK_CPR_SLICE = BIT(3),
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ICP_ACCEL_GEN6_MASK_DCPRZ_SLICE = BIT(4),
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ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE = BIT(6),
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};
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void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data);
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void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data);
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#endif /* ADF_6XXX_HW_DATA_H_ */
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@@ -0,0 +1,224 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2025 Intel Corporation */
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#include <linux/array_size.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <adf_accel_devices.h>
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#include <adf_cfg.h>
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#include <adf_common_drv.h>
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#include <adf_dbgfs.h>
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#include "adf_gen6_shared.h"
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#include "adf_6xxx_hw_data.h"
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static int bar_map[] = {
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0, /* SRAM */
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2, /* PMISC */
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4, /* ETR */
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};
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static void adf_device_down(void *accel_dev)
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{
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adf_dev_down(accel_dev);
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}
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static void adf_dbgfs_cleanup(void *accel_dev)
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{
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adf_dbgfs_exit(accel_dev);
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}
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static void adf_cfg_device_remove(void *accel_dev)
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{
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adf_cfg_dev_remove(accel_dev);
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}
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static void adf_cleanup_hw_data(void *accel_dev)
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{
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struct adf_accel_dev *accel_device = accel_dev;
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if (accel_device->hw_device) {
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adf_clean_hw_data_6xxx(accel_device->hw_device);
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accel_device->hw_device = NULL;
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}
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}
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static void adf_devmgr_remove(void *accel_dev)
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{
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adf_devmgr_rm_dev(accel_dev, NULL);
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}
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static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct adf_accel_pci *accel_pci_dev;
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struct adf_hw_device_data *hw_data;
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struct device *dev = &pdev->dev;
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struct adf_accel_dev *accel_dev;
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struct adf_bar *bar;
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unsigned int i;
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int ret;
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if (num_possible_nodes() > 1 && dev_to_node(dev) < 0) {
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/*
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* If the accelerator is connected to a node with no memory
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* there is no point in using the accelerator since the remote
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* memory transaction will be very slow.
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*/
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return dev_err_probe(dev, -EINVAL, "Invalid NUMA configuration.\n");
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}
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accel_dev = devm_kzalloc(dev, sizeof(*accel_dev), GFP_KERNEL);
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if (!accel_dev)
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return -ENOMEM;
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INIT_LIST_HEAD(&accel_dev->crypto_list);
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INIT_LIST_HEAD(&accel_dev->list);
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accel_pci_dev = &accel_dev->accel_pci_dev;
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accel_pci_dev->pci_dev = pdev;
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accel_dev->owner = THIS_MODULE;
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hw_data = devm_kzalloc(dev, sizeof(*hw_data), GFP_KERNEL);
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if (!hw_data)
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return -ENOMEM;
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pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
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pci_read_config_dword(pdev, ADF_GEN6_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);
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pci_read_config_dword(pdev, ADF_GEN6_FUSECTL0_OFFSET, &hw_data->fuses[ADF_FUSECTL0]);
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pci_read_config_dword(pdev, ADF_GEN6_FUSECTL1_OFFSET, &hw_data->fuses[ADF_FUSECTL1]);
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if (!(hw_data->fuses[ADF_FUSECTL1] & ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE))
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return dev_err_probe(dev, -EFAULT, "Wireless mode is not supported.\n");
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/* Enable PCI device */
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ret = pcim_enable_device(pdev);
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if (ret)
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return dev_err_probe(dev, ret, "Cannot enable PCI device.\n");
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ret = adf_devmgr_add_dev(accel_dev, NULL);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to add new accelerator device.\n");
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ret = devm_add_action_or_reset(dev, adf_devmgr_remove, accel_dev);
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if (ret)
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return ret;
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accel_dev->hw_device = hw_data;
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adf_init_hw_data_6xxx(accel_dev->hw_device);
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ret = devm_add_action_or_reset(dev, adf_cleanup_hw_data, accel_dev);
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if (ret)
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return ret;
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/* Get Accelerators and Accelerator Engine masks */
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hw_data->accel_mask = hw_data->get_accel_mask(hw_data);
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hw_data->ae_mask = hw_data->get_ae_mask(hw_data);
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accel_pci_dev->sku = hw_data->get_sku(hw_data);
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/* If the device has no acceleration engines then ignore it */
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if (!hw_data->accel_mask || !hw_data->ae_mask ||
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(~hw_data->ae_mask & ADF_GEN6_ACCELERATORS_MASK)) {
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ret = -EFAULT;
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return dev_err_probe(dev, ret, "No acceleration units were found.\n");
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}
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/* Create device configuration table */
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ret = adf_cfg_dev_add(accel_dev);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, adf_cfg_device_remove, accel_dev);
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if (ret)
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return ret;
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/* Set DMA identifier */
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
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if (ret)
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return dev_err_probe(dev, ret, "No usable DMA configuration.\n");
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ret = adf_gen6_cfg_dev_init(accel_dev);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to initialize configuration.\n");
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/* Get accelerator capability mask */
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hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);
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if (!hw_data->accel_capabilities_mask) {
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ret = -EINVAL;
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return dev_err_probe(dev, ret, "Failed to get capabilities mask.\n");
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}
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for (i = 0; i < ARRAY_SIZE(bar_map); i++) {
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bar = &accel_pci_dev->pci_bars[i];
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/* Map 64-bit PCIe BAR */
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bar->virt_addr = pcim_iomap_region(pdev, bar_map[i], pci_name(pdev));
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if (!bar->virt_addr) {
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ret = -ENOMEM;
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return dev_err_probe(dev, ret, "Failed to ioremap PCI region.\n");
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}
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}
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pci_set_master(pdev);
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/*
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* The PCI config space is saved at this point and will be restored
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* after a Function Level Reset (FLR) as the FLR does not completely
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* restore it.
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*/
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ret = pci_save_state(pdev);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to save pci state.\n");
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adf_dbgfs_init(accel_dev);
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ret = devm_add_action_or_reset(dev, adf_dbgfs_cleanup, accel_dev);
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if (ret)
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return ret;
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ret = adf_dev_up(accel_dev, true);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, adf_device_down, accel_dev);
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if (ret)
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return ret;
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ret = adf_sysfs_init(accel_dev);
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return ret;
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}
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static void adf_shutdown(struct pci_dev *pdev)
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{
|
||||
struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);
|
||||
|
||||
adf_dev_down(accel_dev);
|
||||
}
|
||||
|
||||
static const struct pci_device_id adf_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QAT_6XXX) },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, adf_pci_tbl);
|
||||
|
||||
static struct pci_driver adf_driver = {
|
||||
.id_table = adf_pci_tbl,
|
||||
.name = ADF_6XXX_DEVICE_NAME,
|
||||
.probe = adf_probe,
|
||||
.shutdown = adf_shutdown,
|
||||
.sriov_configure = adf_sriov_configure,
|
||||
.err_handler = &adf_err_handler,
|
||||
};
|
||||
module_pci_driver(adf_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Intel");
|
||||
MODULE_FIRMWARE(ADF_6XXX_FW);
|
||||
MODULE_FIRMWARE(ADF_6XXX_MMP);
|
||||
MODULE_DESCRIPTION("Intel(R) QuickAssist Technology for GEN6 Devices");
|
||||
MODULE_SOFTDEP("pre: crypto-intel_qat");
|
||||
MODULE_IMPORT_NS("CRYPTO_QAT");
|
||||
@@ -19,6 +19,7 @@ intel_qat-y := adf_accel_engine.o \
|
||||
adf_gen4_pm.o \
|
||||
adf_gen4_ras.o \
|
||||
adf_gen4_vf_mig.o \
|
||||
adf_gen6_shared.o \
|
||||
adf_hw_arbiter.o \
|
||||
adf_init.o \
|
||||
adf_isr.o \
|
||||
|
||||
@@ -26,6 +26,7 @@
|
||||
#define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
|
||||
#define ADF_4XXX_DEVICE_NAME "4xxx"
|
||||
#define ADF_420XX_DEVICE_NAME "420xx"
|
||||
#define ADF_6XXX_DEVICE_NAME "6xxx"
|
||||
#define PCI_DEVICE_ID_INTEL_QAT_4XXX 0x4940
|
||||
#define PCI_DEVICE_ID_INTEL_QAT_4XXXIOV 0x4941
|
||||
#define PCI_DEVICE_ID_INTEL_QAT_401XX 0x4942
|
||||
@@ -35,6 +36,7 @@
|
||||
#define PCI_DEVICE_ID_INTEL_QAT_420XX 0x4946
|
||||
#define PCI_DEVICE_ID_INTEL_QAT_420XXIOV 0x4947
|
||||
#define PCI_DEVICE_ID_INTEL_QAT_6XXX 0x4948
|
||||
#define PCI_DEVICE_ID_INTEL_QAT_6XXX_IOV 0x4949
|
||||
|
||||
#define ADF_DEVICE_FUSECTL_OFFSET 0x40
|
||||
#define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
|
||||
|
||||
@@ -48,6 +48,7 @@ enum adf_device_type {
|
||||
DEV_C3XXXVF,
|
||||
DEV_4XXX,
|
||||
DEV_420XX,
|
||||
DEV_6XXX,
|
||||
};
|
||||
|
||||
struct adf_dev_status_info {
|
||||
|
||||
@@ -8,6 +8,7 @@ enum adf_fw_objs {
|
||||
ADF_FW_ASYM_OBJ,
|
||||
ADF_FW_DC_OBJ,
|
||||
ADF_FW_ADMIN_OBJ,
|
||||
ADF_FW_CY_OBJ,
|
||||
};
|
||||
|
||||
struct adf_fw_config {
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright(c) 2025 Intel Corporation */
|
||||
#ifndef ADF_GEN6_PM_H
|
||||
#define ADF_GEN6_PM_H
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
struct adf_accel_dev;
|
||||
|
||||
/* Power management */
|
||||
#define ADF_GEN6_PM_POLL_DELAY_US 20
|
||||
#define ADF_GEN6_PM_POLL_TIMEOUT_US USEC_PER_SEC
|
||||
#define ADF_GEN6_PM_STATUS 0x50A00C
|
||||
#define ADF_GEN6_PM_INTERRUPT 0x50A028
|
||||
|
||||
/* Power management source in ERRSOU2 and ERRMSK2 */
|
||||
#define ADF_GEN6_PM_SOU BIT(18)
|
||||
|
||||
/* cpm_pm_interrupt bitfields */
|
||||
#define ADF_GEN6_PM_DRV_ACTIVE BIT(20)
|
||||
|
||||
#define ADF_GEN6_PM_DEFAULT_IDLE_FILTER 0x6
|
||||
|
||||
/* cpm_pm_status bitfields */
|
||||
#define ADF_GEN6_PM_INIT_STATE BIT(21)
|
||||
|
||||
#endif /* ADF_GEN6_PM_H */
|
||||
@@ -0,0 +1,49 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/* Copyright(c) 2025 Intel Corporation */
|
||||
#include <linux/export.h>
|
||||
|
||||
#include "adf_gen4_config.h"
|
||||
#include "adf_gen4_hw_csr_data.h"
|
||||
#include "adf_gen4_pfvf.h"
|
||||
#include "adf_gen6_shared.h"
|
||||
|
||||
struct adf_accel_dev;
|
||||
struct adf_pfvf_ops;
|
||||
struct adf_hw_csr_ops;
|
||||
|
||||
/*
|
||||
* QAT GEN4 and GEN6 devices often differ in terms of supported features,
|
||||
* options and internal logic. However, some of the mechanisms and register
|
||||
* layout are shared between those two GENs. This file serves as an abstraction
|
||||
* layer that allows to use existing GEN4 implementation that is also
|
||||
* applicable to GEN6 without additional overhead and complexity.
|
||||
*/
|
||||
void adf_gen6_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)
|
||||
{
|
||||
adf_gen4_init_pf_pfvf_ops(pfvf_ops);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(adf_gen6_init_pf_pfvf_ops);
|
||||
|
||||
void adf_gen6_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
|
||||
{
|
||||
return adf_gen4_init_hw_csr_ops(csr_ops);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(adf_gen6_init_hw_csr_ops);
|
||||
|
||||
int adf_gen6_cfg_dev_init(struct adf_accel_dev *accel_dev)
|
||||
{
|
||||
return adf_gen4_cfg_dev_init(accel_dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(adf_gen6_cfg_dev_init);
|
||||
|
||||
int adf_gen6_comp_dev_config(struct adf_accel_dev *accel_dev)
|
||||
{
|
||||
return adf_comp_dev_config(accel_dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(adf_gen6_comp_dev_config);
|
||||
|
||||
int adf_gen6_no_dev_config(struct adf_accel_dev *accel_dev)
|
||||
{
|
||||
return adf_no_dev_config(accel_dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(adf_gen6_no_dev_config);
|
||||
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright(c) 2025 Intel Corporation */
|
||||
#ifndef ADF_GEN6_SHARED_H_
|
||||
#define ADF_GEN6_SHARED_H_
|
||||
|
||||
struct adf_hw_csr_ops;
|
||||
struct adf_accel_dev;
|
||||
struct adf_pfvf_ops;
|
||||
|
||||
void adf_gen6_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops);
|
||||
void adf_gen6_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
|
||||
int adf_gen6_cfg_dev_init(struct adf_accel_dev *accel_dev);
|
||||
int adf_gen6_comp_dev_config(struct adf_accel_dev *accel_dev);
|
||||
int adf_gen6_no_dev_config(struct adf_accel_dev *accel_dev);
|
||||
#endif/* ADF_GEN6_SHARED_H_ */
|
||||
Reference in New Issue
Block a user