2017-11-01 15:07:57 +01:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
2008-10-22 22:26:29 -07:00
|
|
|
#ifndef _ASM_X86_MICROCODE_H
|
|
|
|
|
#define _ASM_X86_MICROCODE_H
|
2008-08-20 00:22:26 +02:00
|
|
|
|
2025-04-30 22:42:41 -07:00
|
|
|
#include <asm/msr.h>
|
|
|
|
|
|
2008-09-23 12:08:44 +02:00
|
|
|
struct cpu_signature {
|
|
|
|
|
unsigned int sig;
|
|
|
|
|
unsigned int pf;
|
|
|
|
|
unsigned int rev;
|
|
|
|
|
};
|
2008-07-28 18:44:21 +02:00
|
|
|
|
2008-08-20 00:22:26 +02:00
|
|
|
struct ucode_cpu_info {
|
2009-05-11 23:48:27 +02:00
|
|
|
struct cpu_signature cpu_sig;
|
|
|
|
|
void *mc;
|
2008-07-28 18:44:15 +02:00
|
|
|
};
|
2015-02-09 21:42:34 +01:00
|
|
|
|
2015-10-20 11:54:45 +02:00
|
|
|
#ifdef CONFIG_MICROCODE
|
2023-08-12 21:58:47 +02:00
|
|
|
void load_ucode_bsp(void);
|
|
|
|
|
void load_ucode_ap(void);
|
2022-04-19 09:52:41 -07:00
|
|
|
void microcode_bsp_resume(void);
|
2025-04-14 11:59:33 +02:00
|
|
|
bool __init microcode_loader_disabled(void);
|
2012-12-20 23:44:25 -08:00
|
|
|
#else
|
2023-08-12 21:58:47 +02:00
|
|
|
static inline void load_ucode_bsp(void) { }
|
|
|
|
|
static inline void load_ucode_ap(void) { }
|
|
|
|
|
static inline void microcode_bsp_resume(void) { }
|
2025-04-14 11:59:33 +02:00
|
|
|
static inline bool __init microcode_loader_disabled(void) { return false; }
|
2012-12-20 23:44:25 -08:00
|
|
|
#endif
|
2016-02-03 12:33:29 +01:00
|
|
|
|
2023-10-17 23:23:31 +02:00
|
|
|
extern unsigned long initrd_start_early;
|
|
|
|
|
|
2023-08-12 21:58:47 +02:00
|
|
|
#ifdef CONFIG_CPU_SUP_INTEL
|
|
|
|
|
/* Intel specific microcode defines. Public for IFS */
|
|
|
|
|
struct microcode_header_intel {
|
|
|
|
|
unsigned int hdrver;
|
|
|
|
|
unsigned int rev;
|
|
|
|
|
unsigned int date;
|
|
|
|
|
unsigned int sig;
|
|
|
|
|
unsigned int cksum;
|
|
|
|
|
unsigned int ldrver;
|
|
|
|
|
unsigned int pf;
|
|
|
|
|
unsigned int datasize;
|
|
|
|
|
unsigned int totalsize;
|
|
|
|
|
unsigned int metasize;
|
2023-10-02 14:00:11 +02:00
|
|
|
unsigned int min_req_ver;
|
|
|
|
|
unsigned int reserved;
|
2023-08-12 21:58:47 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct microcode_intel {
|
|
|
|
|
struct microcode_header_intel hdr;
|
|
|
|
|
unsigned int bits[];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define DEFAULT_UCODE_DATASIZE (2000)
|
|
|
|
|
#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
|
|
|
|
|
#define MC_HEADER_TYPE_MICROCODE 1
|
|
|
|
|
#define MC_HEADER_TYPE_IFS 2
|
|
|
|
|
|
|
|
|
|
static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr)
|
|
|
|
|
{
|
|
|
|
|
return hdr->datasize ? : DEFAULT_UCODE_DATASIZE;
|
|
|
|
|
}
|
|
|
|
|
|
2026-03-04 10:10:20 -08:00
|
|
|
extern u32 intel_get_platform_id(void);
|
|
|
|
|
|
2023-08-12 21:58:47 +02:00
|
|
|
static inline u32 intel_get_microcode_revision(void)
|
|
|
|
|
{
|
|
|
|
|
u32 rev, dummy;
|
|
|
|
|
|
2025-04-09 22:29:06 +02:00
|
|
|
native_wrmsrq(MSR_IA32_UCODE_REV, 0);
|
2023-08-12 21:58:47 +02:00
|
|
|
|
|
|
|
|
/* As documented in the SDM: Do a CPUID 1 here */
|
|
|
|
|
native_cpuid_eax(1);
|
|
|
|
|
|
|
|
|
|
/* get the current revision from MSR 0x8B */
|
|
|
|
|
native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
|
|
|
|
|
|
|
|
|
|
return rev;
|
|
|
|
|
}
|
|
|
|
|
#endif /* !CONFIG_CPU_SUP_INTEL */
|
|
|
|
|
|
2023-10-02 14:00:05 +02:00
|
|
|
bool microcode_nmi_handler(void);
|
2023-10-02 14:00:08 +02:00
|
|
|
void microcode_offline_nmi_handler(void);
|
2023-10-02 14:00:05 +02:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_MICROCODE_LATE_LOADING
|
|
|
|
|
DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable);
|
|
|
|
|
static __always_inline bool microcode_nmi_handler_enabled(void)
|
|
|
|
|
{
|
|
|
|
|
return static_branch_unlikely(µcode_nmi_handler_enable);
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
static __always_inline bool microcode_nmi_handler_enabled(void) { return false; }
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-10-22 22:26:29 -07:00
|
|
|
#endif /* _ASM_X86_MICROCODE_H */
|