mirror of
https://github.com/linux-msm/debugcc.git
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64ce6ca673
Remove a lot of boilerplate and make the files consistent. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
217 lines
6.6 KiB
C
217 lines
6.6 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/* Copyright (c) 2019, Linaro Ltd. */
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#include <sys/mman.h>
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#include <err.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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#define GCC_BASE 0x01800000
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#define GCC_SIZE 0x80000
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#define GCC_DEBUG_CLK_CTL 0x74000
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#define GCC_CLOCK_FREQ_MEASURE_CTL 0x74004
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#define GCC_CLOCK_FREQ_MEASURE_STATUS 0x74008
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#define GCC_XO_DIV4_CBCR 0x30034
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struct turing_mux {
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struct debug_mux mux;
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unsigned int ahb_reg;
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unsigned int ahb_mask;
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};
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unsigned long measure_turing(const struct measure_clk *clk,
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const struct debug_mux *mux);
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static struct gcc_mux gcc = {
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.mux = {
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.phys = GCC_BASE,
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.size = GCC_SIZE,
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.measure = measure_gcc,
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.enable_reg = GCC_DEBUG_CLK_CTL,
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.enable_mask = BIT(16),
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.mux_reg = GCC_DEBUG_CLK_CTL,
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.mux_mask = 0x1ff,
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.div_reg = GCC_DEBUG_CLK_CTL,
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.div_shift = 12,
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.div_mask = 0xf << 12,
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.div_val = 4,
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},
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.xo_div4_reg = GCC_XO_DIV4_CBCR,
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.debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL,
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.debug_status_reg = GCC_CLOCK_FREQ_MEASURE_STATUS,
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};
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static struct turing_mux turing = {
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.mux = {
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.phys = 0x800000,
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.size = 0x30000,
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.measure = measure_turing,
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.parent = &gcc.mux,
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.parent_mux_val = 50,
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.enable_reg = 0x22008,
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.enable_mask = BIT(0),
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.mux_reg = 0x22000,
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.mux_mask = 0xffff,
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},
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.ahb_reg = 0x5e004,
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.ahb_mask = BIT(31),
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};
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static bool leaf_enabled(struct turing_mux *leaf)
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{
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uint32_t val;
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/* If no AHB clock is specified, we assume it's clocked */
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if (!leaf || !leaf->ahb_mask)
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return true;
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/* we know that the parent is GCC, we read AHB reg from GCC */
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val = readl(leaf->mux.parent->base + leaf->ahb_reg);
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val &= leaf->ahb_mask;
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/* CLK_OFF will be set if block is not clocked, so inverse */
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return !val;
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}
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unsigned long measure_turing(const struct measure_clk *clk,
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const struct debug_mux *mux)
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{
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struct turing_mux *turing = container_of(mux, struct turing_mux, mux);
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if (!leaf_enabled(turing))
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return 0;
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return measure_leaf(clk, mux);
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}
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static struct measure_clk qcs404_clocks[] = {
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{ "snoc_clk", &gcc.mux, 0 },
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{ "gcc_sys_noc_usb3_clk", &gcc.mux, 1 },
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{ "pnoc_clk", &gcc.mux, 8 },
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{ "gcc_pcnoc_usb2_clk", &gcc.mux, 9 },
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{ "gcc_pcnoc_usb3_clk", &gcc.mux, 10 },
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{ "gcc_gp1_clk", &gcc.mux, 16 },
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{ "gcc_gp2_clk", &gcc.mux, 17 },
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{ "gcc_gp3_clk", &gcc.mux, 18 },
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{ "gcc_bimc_gfx_clk", &gcc.mux, 45 },
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{ "aon_clk_src", &turing.mux, 1},
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{ "turing_wrapper_aon_clk", &turing.mux, 2},
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{ "turing_wrapper_cnoc_sway_aon_clk", &turing.mux, 3},
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{ "turing_wrapper_qos_ahbs_aon_clk", &turing.mux, 4},
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{ "q6ss_ahbm_aon_clk", &turing.mux, 5},
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{ "q6ss_ahbs_aon_clk", &turing.mux, 6},
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{ "turing_wrapper_bus_timeout_aon_clk", &turing.mux, 7},
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{ "turing_wrapper_rscc_aon_clk", &turing.mux, 8},
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{ "q6ss_alt_reset_aon_clk", &turing.mux, 10},
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{ "qos_fixed_lat_counter_clk_src", &turing.mux, 11},
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{ "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &turing.mux, 12},
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{ "turing_wrapper_qos_danger_fixed_lat_counter_clk", &turing.mux, 13},
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{ "q6_xo_clk_src", &turing.mux, 14},
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{ "qos_xo_clk_src", &turing.mux, 15},
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{ "turing_wrapper_qos_xo_lat_counter_clk", &turing.mux, 16},
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{ "bcr_slp_clk_src", &turing.mux, 19},
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{ "q6ss_bcr_slp_clk", &turing.mux, 20},
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{ "turing_wrapper_cnoc_ahbs_clk", &turing.mux, 28},
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{ "q6ss_q6_axim_clk", &turing.mux, 29},
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{ "q6ss_sleep_clk_src", &turing.mux, 33},
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{ "qdsp6ss_xo_clk", &turing.mux, 36},
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{ "qdsp6ss_sleep_clk", &turing.mux, 37},
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{ "q6ss_dbg_in_clk", &turing.mux, 39},
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{ "gcc_usb_hs_system_clk", &gcc.mux, 96 },
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{ "gcc_usb_hs_inactivity_timers_clk", &gcc.mux, 98 },
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{ "gcc_usb2a_phy_sleep_clk", &gcc.mux, 99 },
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{ "gcc_usb_hs_phy_cfg_ahb_clk", &gcc.mux, 100 },
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{ "gcc_usb20_mock_utmi_clk", &gcc.mux, 101 },
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{ "gcc_sdcc1_apps_clk", &gcc.mux, 104 },
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{ "gcc_sdcc1_ahb_clk", &gcc.mux, 105 },
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{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 106 },
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{ "gcc_sdcc2_apps_clk", &gcc.mux, 112 },
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{ "gcc_sdcc2_ahb_clk", &gcc.mux, 113 },
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{ "gcc_usb30_master_clk", &gcc.mux, 120 },
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{ "gcc_usb30_sleep_clk", &gcc.mux, 121 },
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{ "gcc_usb30_mock_utmi_clk", &gcc.mux, 122 },
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{ "gcc_usb3_phy_pipe_clk", &gcc.mux, 123 },
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{ "gcc_usb3_phy_aux_clk", &gcc.mux, 124 },
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{ "gcc_eth_axi_clk", &gcc.mux, 128 },
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{ "gcc_eth_rgmii_clk", &gcc.mux, 129 },
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{ "gcc_eth_slave_ahb_clk", &gcc.mux, 130 },
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{ "gcc_eth_ptp_clk", &gcc.mux, 131 },
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{ "gcc_blsp1_ahb_clk", &gcc.mux, 136 },
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{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 138 },
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{ "wcnss_m_clk", &gcc.mux, 138 },
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{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 139 },
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{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 140 },
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{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 142 },
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{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 143 },
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{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 144 },
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{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 146 },
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{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 147 },
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{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 148 },
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{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 149 },
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{ "gcc_blsp1_uart3_apps_clk", &gcc.mux, 150 },
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{ "gcc_blsp1_qup0_spi_apps_clk", &gcc.mux, 152 },
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{ "gcc_blsp1_qup0_i2c_apps_clk", &gcc.mux, 153 },
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{ "gcc_blsp1_uart0_apps_clk", &gcc.mux, 154 },
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{ "gcc_blsp2_ahb_clk", &gcc.mux, 160 },
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{ "gcc_blsp2_qup0_i2c_apps_clk", &gcc.mux, 162 },
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{ "gcc_blsp2_qup0_spi_apps_clk", &gcc.mux, 163 },
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{ "gcc_blsp2_uart0_apps_clk", &gcc.mux, 164 },
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{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 168 },
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{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 169 },
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{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 170 },
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{ "gcc_pcie_0_aux_clk", &gcc.mux, 171 },
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{ "gcc_pcie_0_pipe_clk", &gcc.mux, 172 },
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//{ "pcie0_pipe_clk", &gcc.mux, 173, 1 },
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{ "qpic_clk", &gcc.mux, 192 },
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{ "gcc_pdm_ahb_clk", &gcc.mux, 208 },
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{ "gcc_pdm2_clk", &gcc.mux, 210 },
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{ "gcc_pwm0_xo512_clk", &gcc.mux, 211 },
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{ "gcc_pwm1_xo512_clk", &gcc.mux, 212 },
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{ "gcc_pwm2_xo512_clk", &gcc.mux, 213 },
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{ "gcc_prng_ahb_clk", &gcc.mux, 216 },
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{ "gcc_geni_ir_s_clk", &gcc.mux, 238 },
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{ "gcc_boot_rom_ahb_clk", &gcc.mux, 248 },
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{ "ce1_clk", &gcc.mux, 312 },
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{ "bimc_clk", &gcc.mux, 346 },
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//{ "bimc_fsm_ddr_clk", &gcc.mux, 350, 1 },
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{ "gcc_apss_ahb_clk", &gcc.mux, 360 },
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{ "gcc_dcc_clk", &gcc.mux, 441 },
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{ "gcc_oxili_gfx3d_clk", &gcc.mux, 490 },
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{ "gcc_oxili_ahb_clk", &gcc.mux, 491 },
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{ "gcc_mdss_hdmi_pclk_clk", &gcc.mux, 497 },
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{ "gcc_mdss_hdmi_app_clk", &gcc.mux, 498 },
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{ "gcc_mdss_ahb_clk", &gcc.mux, 502 },
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{ "gcc_mdss_axi_clk", &gcc.mux, 503 },
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{ "gcc_mdss_pclk0_clk", &gcc.mux, 504 },
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{ "gcc_mdss_mdp_clk", &gcc.mux, 505 },
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{ "gcc_mdss_vsync_clk", &gcc.mux, 507 },
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{ "gcc_mdss_byte0_clk", &gcc.mux, 508 },
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{ "gcc_mdss_esc0_clk", &gcc.mux, 509 },
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{}
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};
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struct debugcc_platform qcs404_debugcc = {
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"qcs404",
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qcs404_clocks,
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};
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