diff --git a/src/xenia/cpu/backend/a64/a64_sequences.cc b/src/xenia/cpu/backend/a64/a64_sequences.cc
index 63269dbee..4297314ad 100644
--- a/src/xenia/cpu/backend/a64/a64_sequences.cc
+++ b/src/xenia/cpu/backend/a64/a64_sequences.cc
@@ -898,8 +898,7 @@ struct COMPARE_EQ_F32
     : Sequence<COMPARE_EQ_F32, I<OPCODE_COMPARE_EQ, I8Op, F32Op, F32Op>> {
   static void Emit(A64Emitter& e, const EmitArgType& i) {
     EmitCommutativeBinaryVOp<SReg>(
-        e, i,
-        [&i](A64Emitter& e, I8Op dest, const SReg& src1, const SReg& src2) {
+        e, i, [](A64Emitter& e, I8Op dest, const SReg& src1, const SReg& src2) {
           e.FCMP(src1, src2);
         });
     e.CSET(i.dest, Cond::EQ);
@@ -909,8 +908,7 @@ struct COMPARE_EQ_F64
     : Sequence<COMPARE_EQ_F64, I<OPCODE_COMPARE_EQ, I8Op, F64Op, F64Op>> {
   static void Emit(A64Emitter& e, const EmitArgType& i) {
     EmitCommutativeBinaryVOp<DReg>(
-        e, i,
-        [&i](A64Emitter& e, I8Op dest, const DReg& src1, const DReg& src2) {
+        e, i, [](A64Emitter& e, I8Op dest, const DReg& src1, const DReg& src2) {
           e.FCMP(src1, src2);
         });
     e.CSET(i.dest, Cond::EQ);
@@ -1794,7 +1792,7 @@ struct MUL_SUB_F32
 
     // Multiply operation is commutative.
     EmitCommutativeBinaryVOp<SReg>(
-        e, i, [&i](A64Emitter& e, SReg dest, SReg src1, SReg src2) {
+        e, i, [](A64Emitter& e, SReg dest, SReg src1, SReg src2) {
           e.FMUL(dest, src1, src2);  // $0 = $1 * $2
         });
 
@@ -1819,7 +1817,7 @@ struct MUL_SUB_F64
 
     // Multiply operation is commutative.
     EmitCommutativeBinaryVOp<DReg>(
-        e, i, [&i](A64Emitter& e, DReg dest, DReg src1, DReg src2) {
+        e, i, [](A64Emitter& e, DReg dest, DReg src1, DReg src2) {
           e.FMUL(dest, src1, src2);  // $0 = $1 * $2
         });
 
@@ -1845,7 +1843,7 @@ struct MUL_SUB_V128
 
     // Multiply operation is commutative.
     EmitCommutativeBinaryVOp(
-        e, i, [&i](A64Emitter& e, QReg dest, QReg src1, QReg src2) {
+        e, i, [](A64Emitter& e, QReg dest, QReg src1, QReg src2) {
           e.FMUL(dest.S4(), src1.S4(), src2.S4());  // $0 = $1 * $2
         });