Richard HendersonandPeter Maydell d3765835ed exec: Add target-specific tlb bits to MemTxAttrs ...

These bits can be used to cache target-specific data in cputlb
read from the page tables.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190128223118.5255-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2019-02-05 16:52:37 +00:00

..

user

…

address-spaces.h

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cpu_ldst_template.h

cputlb: read CPUTLBEntry.addr_write atomically

2018-10-18 19:46:53 -07:00

cpu_ldst_useronly_template.h

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cpu_ldst.h

cputlb: Remove static tlb sizing

2019-01-28 07:04:35 -08:00

cpu-all.h

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cpu-common.h

Rename cpu_physical_memory_write_rom() to address_space_write_rom()

2018-12-14 13:30:48 +00:00

cpu-defs.h

cputlb: Remove static tlb sizing

2019-01-28 07:04:35 -08:00

cputlb.h

cputlb: Count "partial" and "elided" tlb flushes

2018-10-31 12:16:30 +00:00

exec-all.h

accel/tcg: Add cluster number to TCG TB hash

2019-01-29 11:46:06 +00:00

gdbstub.h

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gen-icount.h

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helper-gen.h

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helper-head.h

tcg: Add TCG_CALL_NO_RETURN

2018-12-26 06:40:24 +11:00

helper-proto.h

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helper-tcg.h

tcg: Add TCG_CALL_NO_RETURN

2018-12-26 06:40:24 +11:00

hwaddr.h

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ioport.h

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log.h

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memattrs.h

exec: Add target-specific tlb bits to MemTxAttrs

2019-02-05 16:52:37 +00:00

memory_ldst_cached.inc.h

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memory_ldst_phys.inc.h

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memory_ldst.inc.h

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memory-internal.h

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memory.h

memory: add memory_region_flush_rom_device()

2019-01-29 11:46:04 +00:00

poison.h

exec: Add RISC-V GCC poison macro

2018-12-26 06:40:02 +11:00

ram_addr.h

COLO: Load dirty pages into SVM's RAM cache firstly

2018-10-19 11:15:03 +08:00

ramlist.h

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semihost.h

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softmmu-semi.h

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target_page.h

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tb-context.h

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tb-hash.h

include: move exec/tb-hash-xx.h to qemu/xxhash.h

2018-12-17 06:04:44 +03:00

tb-lookup.h

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translator.h

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