Peter Maydell bbe165740a Merge remote-tracking branch 'remotes/vivier2/tags/ppc-for-4.2-pull-request' into staging ...

ppc patch queue 2019-11-15

Several fixes for 4.2.0-rc2:

fix mos6522 performance issue,
xive/xics issues,
fix /chosen device-tree on reset
and KVM default cpu-model for all machine classes

# gpg: Signature made Mon 18 Nov 2019 10:52:19 GMT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "lvivier@redhat.com"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/ppc-for-4.2-pull-request:
  mos6522: fix T1 and T2 timers
  spapr/kvm: Set default cpu model for all machine classes
  spapr: Add /chosen to FDT only at reset time to preserve kernel and initramdisk
  ppc: Skip partially initialized vCPUs in 'info pic'
  xive, xics: Fix reference counting on CPU objects
  ppc: Add intc_destroy() handlers to SpaprInterruptController/PnvChip

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2019-11-18 11:09:06 +00:00

..

alpha

target/alpha: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

arm

target/arm: Allow reading flags from FPSCR for M-profile

2019-11-01 20:41:00 +00:00

cris

cputlb: ensure _cmmu helper functions follow the naming standard

2019-10-28 15:12:38 +00:00

hppa

target/hppa: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

i386

target/i386: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

lm32

…

m68k

target/m68k: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

microblaze

target/microblaze: Plug temp leak around eval_cond_jmp()

2019-11-12 16:35:26 +01:00

mips

target/mips: Refactor handling of vector compare 'less than' (signed) instructions

2019-10-25 18:37:01 +02:00

moxie

…

nios2

…

openrisc

target/openrisc: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

ppc

spapr/kvm: Set default cpu model for all machine classes

2019-11-18 11:50:39 +01:00

riscv

target/riscv: Remove atomic accesses to MIP CSR

2019-11-14 09:53:28 -08:00

s390x

s390x/kvm: Set default cpu model for all machine classes

2019-10-21 18:03:08 +02:00

sh4

target/sh4: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

sparc

target/sparc: Define an enumeration for accessing env->regwptr

2019-11-06 13:35:25 +01:00

tilegx

tcg: TCGMemOp is now accelerator independent MemOp

2019-09-03 08:30:38 -07:00

tricore

tcg: TCGMemOp is now accelerator independent MemOp

2019-09-03 08:30:38 -07:00

unicore32

…

xtensa

target/xtensa: fetch code with translator_ld

2019-10-28 15:12:38 +00:00