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https://github.com/izzy2lost/xemu.git
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37897b29b3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20251008215613.300150-69-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
257 lines
9.2 KiB
C
257 lines
9.2 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "user/cpu_loop.h"
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#include "signal-common.h"
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#include "qemu/guest-random.h"
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#include "semihosting/common-semi.h"
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#include "target/arm/syndrome.h"
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#include "target/arm/cpu-features.h"
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/* Use the exception syndrome to map a cpu exception to a signal. */
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static void signal_for_exception(CPUARMState *env, vaddr addr)
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{
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uint32_t syn = env->exception.syndrome;
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int si_code, si_signo;
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/* Let signal delivery see that ESR is live. */
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env->cp15.esr_el[1] = syn;
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switch (syn_get_ec(syn)) {
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case EC_DATAABORT:
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case EC_INSNABORT:
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/* Both EC have the same format for FSC, or close enough. */
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switch (extract32(syn, 0, 6)) {
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case 0x04 ... 0x07: /* Translation fault, level {0-3} */
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si_signo = TARGET_SIGSEGV;
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si_code = TARGET_SEGV_MAPERR;
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break;
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case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
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case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
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si_signo = TARGET_SIGSEGV;
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si_code = TARGET_SEGV_ACCERR;
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break;
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case 0x11: /* Synchronous Tag Check Fault */
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si_signo = TARGET_SIGSEGV;
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si_code = TARGET_SEGV_MTESERR;
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break;
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case 0x21: /* Alignment fault */
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si_signo = TARGET_SIGBUS;
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si_code = TARGET_BUS_ADRALN;
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case EC_PCALIGNMENT:
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si_signo = TARGET_SIGBUS;
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si_code = TARGET_BUS_ADRALN;
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break;
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case EC_UNCATEGORIZED: /* E.g. undefined instruction */
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case EC_SYSTEMREGISTERTRAP: /* E.g. inaccessible register */
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case EC_SMETRAP: /* E.g. invalid insn in streaming state */
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case EC_BTITRAP: /* E.g. invalid guarded branch target */
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case EC_ILLEGALSTATE:
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/*
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* Illegal state happens via an ERET from a privileged mode,
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* so is not normally possible from user-only. However, gdbstub
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* is not prevented from writing CPSR_IL, aka PSTATE.IL, which
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* would generate a trap from the next translated block.
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* In the kernel, default case -> el0_inv -> bad_el0_sync.
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*/
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si_signo = TARGET_SIGILL;
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si_code = TARGET_ILL_ILLOPC;
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break;
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case EC_PACFAIL:
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si_signo = TARGET_SIGILL;
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si_code = TARGET_ILL_ILLOPN;
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break;
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case EC_GCS:
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si_signo = TARGET_SIGSEGV;
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si_code = TARGET_SEGV_CPERR;
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break;
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case EC_MOP:
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/*
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* FIXME: The kernel fixes up wrong-option exceptions.
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* For QEMU linux-user mode, you can only get these if
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* the process is doing something silly (not executing
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* the MOPS instructions in the required P/M/E sequence),
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* so it is not a problem in practice that we do not.
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*
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* We ought ideally to implement the same "rewind to the
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* start of the sequence" logic that the kernel does in
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* arm64_mops_reset_regs(). In the meantime, deliver
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* the guest a SIGILL, with the same ILLOPN si_code
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* we've always used for this.
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*/
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si_signo = TARGET_SIGILL;
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si_code = TARGET_ILL_ILLOPN;
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break;
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case EC_WFX_TRAP: /* user-only WFI implemented as NOP */
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case EC_CP15RTTRAP: /* AArch32 */
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case EC_CP15RRTTRAP: /* AArch32 */
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case EC_CP14RTTRAP: /* AArch32 */
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case EC_CP14DTTRAP: /* AArch32 */
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case EC_ADVSIMDFPACCESSTRAP: /* user-only does not disable fpu */
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case EC_FPIDTRAP: /* AArch32 */
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case EC_PACTRAP: /* user-only does not disable pac regs */
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case EC_BXJTRAP: /* AArch32 */
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case EC_CP14RRTTRAP: /* AArch32 */
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case EC_AA32_SVC: /* AArch32 */
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case EC_AA32_HVC: /* AArch32 */
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case EC_AA32_SMC: /* AArch32 */
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case EC_AA64_SVC: /* generates EXCP_SWI */
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case EC_AA64_HVC: /* user-only generates EC_UNCATEGORIZED */
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case EC_AA64_SMC: /* user-only generates EC_UNCATEGORIZED */
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case EC_SVEACCESSTRAP: /* user-only does not disable sve */
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case EC_ERETTRAP: /* user-only generates EC_UNCATEGORIZED */
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case EC_GPC: /* user-only has no EL3 gpc tables */
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case EC_INSNABORT_SAME_EL: /* el0 cannot trap to el0 */
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case EC_DATAABORT_SAME_EL: /* el0 cannot trap to el0 */
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case EC_SPALIGNMENT: /* sp alignment checks not implemented */
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case EC_AA32_FPTRAP: /* fp exceptions not implemented */
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case EC_AA64_FPTRAP: /* fp exceptions not implemented */
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case EC_SERROR: /* user-only does not have hw faults */
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case EC_BREAKPOINT: /* user-only does not have hw debug */
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case EC_BREAKPOINT_SAME_EL: /* user-only does not have hw debug */
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case EC_SOFTWARESTEP: /* user-only does not have hw debug */
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case EC_SOFTWARESTEP_SAME_EL: /* user-only does not have hw debug */
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case EC_WATCHPOINT: /* user-only does not have hw debug */
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case EC_WATCHPOINT_SAME_EL: /* user-only does not have hw debug */
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case EC_AA32_BKPT: /* AArch32 */
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case EC_VECTORCATCH: /* AArch32 */
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case EC_AA64_BKPT: /* generates EXCP_BKPT */
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default:
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g_assert_not_reached();
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}
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force_sig_fault(si_signo, si_code, addr);
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}
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/* AArch64 main loop */
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void cpu_loop(CPUARMState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr;
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abi_long ret;
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for (;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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qemu_process_cpu_events(cs);
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switch (trapnr) {
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case EXCP_SWI:
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/* On syscall, PSTATE.ZA is preserved, PSTATE.SM is cleared. */
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aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
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ret = do_syscall(env,
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env->xregs[8],
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env->xregs[0],
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env->xregs[1],
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env->xregs[2],
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env->xregs[3],
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env->xregs[4],
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env->xregs[5],
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0, 0);
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if (ret == -QEMU_ERESTARTSYS) {
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env->pc -= 4;
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} else if (ret != -QEMU_ESIGRETURN) {
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env->xregs[0] = ret;
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}
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_UDEF:
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signal_for_exception(env, env->pc);
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break;
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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signal_for_exception(env, env->exception.vaddress);
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break;
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case EXCP_DEBUG:
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case EXCP_BKPT:
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
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break;
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case EXCP_SEMIHOST:
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do_common_semihosting(cs);
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env->pc += 4;
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break;
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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}
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/* Check for MTE asynchronous faults */
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if (unlikely(env->cp15.tfsr_el[0])) {
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env->cp15.tfsr_el[0] = 0;
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force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0);
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}
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process_pending_signals(env);
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/* Exception return on AArch64 always clears the exclusive monitor,
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* so any return to running guest code implies this.
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*/
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env->exclusive_addr = -1;
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}
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}
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void init_main_thread(CPUState *cs, struct image_info *info)
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{
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CPUARMState *env = cpu_env(cs);
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ARMCPU *cpu = env_archcpu(env);
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if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
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fprintf(stderr,
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"The selected ARM CPU does not support 64 bit mode\n");
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exit(EXIT_FAILURE);
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}
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env->pc = info->entry & ~0x3ULL;
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env->xregs[31] = info->start_stack;
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#if TARGET_BIG_ENDIAN
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env->cp15.sctlr_el[1] |= SCTLR_E0E;
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for (int i = 1; i < 4; ++i) {
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env->cp15.sctlr_el[i] |= SCTLR_EE;
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}
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arm_rebuild_hflags(env);
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#endif
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
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}
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}
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