Files
Paolo Bonzini d5e1d2dea1 target/i386: clear CPU_INTERRUPT_SIPI for all accelerators
Similar to what commit df32e5c5 did for TCG; fixes boot with multiple
processors on WHPX and probably more accelerators

Fixes: df32e5c568 ("i386/cpu: Prevent delivering SIPI during SMM in TCG mode", 2025-10-14)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3178
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-10-28 14:50:40 +01:00
..
2024-12-20 17:44:56 +01:00