mirror of
https://github.com/izzy2lost/xemu.git
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Shameer KolothumandPeter Maydell
951bc76fb6
Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus. However, when retrieving IOMMU ops for a device using pci_device_get_iommu_bus_devfn(), the function checks the parent_dev and fetches IOMMU ops from the parent device, even if the current bus does not have any associated IOMMU ops. This behavior works for now because QEMU's IOMMU implementations are globally scoped, and host bridges rely on the bypass_iommu property to skip IOMMU translation when needed. However, this model will break with the soon to be introduced arm-smmuv3 device, which allows users to associate the IOMMU with a specific PCIe root complex (e.g., the default pcie.0 or a pxb-pcie root complex). For example, consider the following setup with multiple root complexes: -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0 \ ... -device pxb-pcie,id=pcie.1,bus_nr=8,bus=pcie.0 \ -device pcie-root-port,id=pcie.port1,bus=pcie.1 \ -device virtio-net-pci,bus=pcie.port1 In Qemu, pxb-pcie acts as a special root complex whose parent is effectively the default root complex(pcie.0). Hence, though pcie.1 has no associated SMMUv3 as per above, pci_device_get_iommu_bus_devfn() will incorrectly return the IOMMU ops from pcie.0 due to the fallback via parent_dev. To fix this, introduce a new helper pci_setup_iommu_per_bus() that explicitly sets the new iommu_per_bus field in the PCIBus structure. This helper will be used in a subsequent patch that adds support for the new arm-smmuv3 device. Update pci_device_get_iommu_bus_devfn() to use iommu_per_bus when determining the correct IOMMU ops, ensuring accurate behavior for per-bus IOMMUs. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Message-id: 20250829082543.7680-7-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
#ifndef QEMU_PCI_BUS_H
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#define QEMU_PCI_BUS_H
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#include "hw/pci/pci.h"
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/*
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* PCI Bus datastructures.
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*
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* Do not access the following members directly;
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* use accessor functions in pci.h
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*/
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struct PCIBusClass {
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/*< private >*/
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BusClass parent_class;
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/*< public >*/
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int (*bus_num)(PCIBus *bus);
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uint16_t (*numa_node)(PCIBus *bus);
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};
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enum PCIBusFlags {
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/* This bus is the root of a PCI domain */
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PCI_BUS_IS_ROOT = 0x0001,
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/* PCIe extended configuration space is accessible on this bus */
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PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002,
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/* This is a CXL Type BUS */
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PCI_BUS_CXL = 0x0004,
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};
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#define PCI_NO_PASID UINT32_MAX
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struct PCIBus {
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BusState qbus;
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enum PCIBusFlags flags;
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const PCIIOMMUOps *iommu_ops;
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void *iommu_opaque;
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bool iommu_per_bus;
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uint8_t devfn_min;
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uint32_t slot_reserved_mask;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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pci_route_irq_fn route_intx_to_irq;
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void *irq_opaque;
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PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
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PCIDevice *parent_dev;
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MemoryRegion *address_space_mem;
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MemoryRegion *address_space_io;
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QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
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QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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Notifier machine_done;
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};
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static inline bool pci_bus_is_cxl(PCIBus *bus)
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{
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return !!(bus->flags & PCI_BUS_CXL);
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}
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static inline bool pci_bus_is_root(PCIBus *bus)
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{
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return !!(bus->flags & PCI_BUS_IS_ROOT);
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}
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static inline bool pci_bus_allows_extended_config_space(PCIBus *bus)
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{
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return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE);
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}
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#endif /* QEMU_PCI_BUS_H */
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