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Jamin LinandCédric Le Goater
ba6fb09048
Introduce PCIe config (H2X) support for the AST2700 SoC. Unlike the AST2600, the AST2700 provides three independent Root Complexes, each with its own H2X (AHB to PCIe bridge) register block of size 0x100. All RCs use the same MSI address (0x000000F0). The H2X block includes two different access paths: 1. CFGI (internal bridge): used to access the host bridge itself, always with BDF=0. The AST2700 controller simplifies the design by exposing only one register (H2X_CFGI_TLP) with fields for ADDR[15:0], BEN[19:16], and WR[20]. This is not a full TLP descriptor as in the external case. For QEMU readability and code reuse, the model converts H2X_CFGI_TLP into a standard TLP TX descriptor with BDF forced to 0 and then calls the existing helpers aspeed_pcie_cfg_readwrite() and aspeed_pcie_cfg_translate_write(). 2. CFGE (external EP access): used to access external endpoints. The AST2700 design provides H2X_CFGE_TLP1 and a small FIFO at H2X_CFGE_TLPN. For reads, TX DESC0 is stored in TLP1 and DESC1/DESC2 in TLPN FIFO slots. For writes, TX DESC0 is stored in TLP1, DESC1/DESC2 in TLPN FIFO[0..1], and TX write data in TLPN FIFO[2]. The implementation extends AspeedPCIECfgState with a small FIFO and index, wires up new register definitions for AST2700, and adds a specific ops table and class (TYPE_ASPEED_2700_PCIE_CFG). The reset handler clears the FIFO state. Interrupt and MSI status registers are also supported. This provides enough modeling for firmware and drivers to use any of the three PCIe RCs on AST2700 with their own dedicated H2X config window, while reusing existing TLP decode helpers in QEMU. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
/*
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* ASPEED PCIe Host Controller
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*
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* Copyright (C) 2025 ASPEED Technology Inc.
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* Copyright (c) 2022 Cédric Le Goater <clg@kaod.org>
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*
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* Authors:
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* Cédric Le Goater <clg@kaod.org>
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* Jamin Lin <jamin_lin@aspeedtech.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Based on previous work from Cédric Le Goater.
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* Modifications extend support for the ASPEED AST2600 and AST2700 platforms.
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*/
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#ifndef ASPEED_PCIE_H
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#define ASPEED_PCIE_H
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#include "hw/sysbus.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pcie_port.h"
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#include "qom/object.h"
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typedef struct AspeedPCIECfgTxDesc {
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uint32_t desc0;
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uint32_t desc1;
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uint32_t desc2;
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uint32_t desc3;
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uint32_t wdata;
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uint32_t rdata_reg;
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} AspeedPCIECfgTxDesc;
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typedef struct AspeedPCIERcRegs {
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uint32_t int_en_reg;
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uint32_t int_sts_reg;
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uint32_t msi_sts0_reg;
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uint32_t msi_sts1_reg;
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} AspeedPCIERcRegs;
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typedef struct AspeedPCIERegMap {
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AspeedPCIERcRegs rc;
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} AspeedPCIERegMap;
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#define TYPE_ASPEED_PCIE_ROOT_PORT "aspeed.pcie-root-port"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootPortState, ASPEED_PCIE_ROOT_PORT)
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typedef struct AspeedPCIERootPortState {
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PCIESlot parent_obj;
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} AspeedPCIERootPortState;
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#define TYPE_ASPEED_PCIE_ROOT_DEVICE "aspeed.pcie-root-device"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootDeviceState, ASPEED_PCIE_ROOT_DEVICE);
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struct AspeedPCIERootDeviceState {
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PCIBridge parent_obj;
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};
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#define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC);
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struct AspeedPCIERcState {
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PCIExpressHost parent_obj;
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MemoryRegion iommu_root;
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AddressSpace iommu_as;
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MemoryRegion dram_alias;
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MemoryRegion *dram_mr;
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MemoryRegion mmio_window;
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MemoryRegion msi_window;
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MemoryRegion io_window;
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MemoryRegion mmio;
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MemoryRegion io;
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uint64_t dram_base;
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uint32_t msi_addr;
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uint32_t rp_addr;
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uint32_t bus_nr;
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char name[16];
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bool has_rd;
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qemu_irq irq;
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AspeedPCIERootDeviceState root_device;
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AspeedPCIERootPortState root_port;
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};
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/* Bridge between AHB bus and PCIe RC. */
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#define TYPE_ASPEED_PCIE_CFG "aspeed.pcie-cfg"
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#define TYPE_ASPEED_2700_PCIE_CFG TYPE_ASPEED_PCIE_CFG "-ast2700"
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OBJECT_DECLARE_TYPE(AspeedPCIECfgState, AspeedPCIECfgClass, ASPEED_PCIE_CFG);
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struct AspeedPCIECfgState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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uint32_t *regs;
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uint32_t id;
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const AspeedPCIERcRegs *rc_regs;
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AspeedPCIERcState rc;
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uint32_t tlpn_fifo[3];
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uint32_t tlpn_idx;
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};
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struct AspeedPCIECfgClass {
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SysBusDeviceClass parent_class;
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const AspeedPCIERegMap *reg_map;
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const MemoryRegionOps *reg_ops;
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uint32_t rc_msi_addr;
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uint32_t rc_rp_addr;
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uint64_t rc_bus_nr;
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uint64_t nr_regs;
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bool rc_has_rd;
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};
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#define TYPE_ASPEED_PCIE_PHY "aspeed.pcie-phy"
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#define TYPE_ASPEED_2700_PCIE_PHY TYPE_ASPEED_PCIE_PHY "-ast2700"
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OBJECT_DECLARE_TYPE(AspeedPCIEPhyState, AspeedPCIEPhyClass, ASPEED_PCIE_PHY);
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struct AspeedPCIEPhyState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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uint32_t *regs;
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uint32_t id;
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};
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struct AspeedPCIEPhyClass {
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SysBusDeviceClass parent_class;
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uint64_t nr_regs;
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};
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#endif /* ASPEED_PCIE_H */
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