mirror of
https://github.com/izzy2lost/xemu.git
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Jamin LinandCédric Le Goater
bbdd4167fa
Refactor the AST27x0 TSP implementation to derive from the newly introduced AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class includes SoC-level infrastructure and peripheral definitions that are not applicable to lightweight coprocessor subsystems such as TSP, resulting in unnecessary coupling and complexity. This change moves the Aspeed27x0TSPSoCState structure definition into aspeed_coprocessor.h and updates all related references in aspeed_ast27x0-tsp.c and aspeed_ast27x0-fc.c to use AspeedCoprocessorState and AspeedCoprocessorClass. Key updates include: - Replace inheritance from AspeedSoC -> AspeedCoprocessor. - Update type casts and macros from ASPEED_SOC_* to ASPEED_COPROCESSOR_* This refactor improves modularity, reduces memory footprint, and prepares for future coprocessor variants to share a lighter-weight common base. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
316 lines
8.3 KiB
C
316 lines
8.3 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_SOC_H
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#define ASPEED_SOC_H
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#include "hw/cpu/a15mpcore.h"
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#include "hw/arm/armv7m.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/intc/aspeed_intc.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/adc/aspeed_adc.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/misc/aspeed_xdma.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/rtc/aspeed_rtc.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/misc/aspeed_i3c.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/misc/aspeed_hace.h"
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#include "hw/misc/aspeed_sbc.h"
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#include "hw/misc/aspeed_sli.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#include "hw/net/ftgmac100.h"
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#include "target/arm/cpu.h"
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#include "hw/gpio/aspeed_gpio.h"
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#include "hw/sd/aspeed_sdhci.h"
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#include "hw/usb/hcd-ehci.h"
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#include "qom/object.h"
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#include "hw/misc/aspeed_lpc.h"
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#include "hw/misc/unimp.h"
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#include "hw/pci-host/aspeed_pcie.h"
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#include "hw/misc/aspeed_peci.h"
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#include "hw/fsi/aspeed_apb2opb.h"
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#include "hw/char/serial-mm.h"
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#include "hw/intc/arm_gicv3.h"
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#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
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#define ASPEED_SPIS_NUM 3
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#define ASPEED_EHCIS_NUM 4
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#define ASPEED_WDTS_NUM 8
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#define ASPEED_CPUS_NUM 4
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#define ASPEED_MACS_NUM 4
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#define ASPEED_UARTS_NUM 13
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#define ASPEED_JTAG_NUM 2
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#define ASPEED_PCIE_NUM 3
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struct AspeedSoCState {
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DeviceState parent;
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MemoryRegion *memory;
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MemoryRegion *dram_mr;
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MemoryRegion dram_container;
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MemoryRegion sram;
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MemoryRegion spi_boot_container;
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MemoryRegion spi_boot;
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MemoryRegion vbootrom;
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MemoryRegion pcie_mmio_alias[ASPEED_PCIE_NUM];
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AddressSpace dram_as;
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AspeedRtcState rtc;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedI3CState i3c;
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AspeedSCUState scu;
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AspeedSCUState scuio;
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AspeedHACEState hace;
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AspeedXDMAState xdma;
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AspeedADCState adc;
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AspeedSMCState fmc;
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AspeedSMCState spi[ASPEED_SPIS_NUM];
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EHCISysBusState ehci[ASPEED_EHCIS_NUM];
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AspeedSBCState sbc;
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AspeedSLIState sli;
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AspeedSLIState sliio;
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MemoryRegion secsram;
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UnimplementedDeviceState sbc_unimplemented;
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AspeedSDMCState sdmc;
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AspeedWDTState wdt[ASPEED_WDTS_NUM];
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FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
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AspeedMiiState mii[ASPEED_MACS_NUM];
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AspeedGPIOState gpio;
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AspeedGPIOState gpio_1_8v;
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AspeedSDHCIState sdhci;
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AspeedSDHCIState emmc;
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AspeedLPCState lpc;
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AspeedPCIECfgState pcie[ASPEED_PCIE_NUM];
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AspeedPCIEPhyState pcie_phy[ASPEED_PCIE_NUM];
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AspeedPECIState peci;
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SerialMM uart[ASPEED_UARTS_NUM];
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Clock *sysclk;
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UnimplementedDeviceState iomem;
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UnimplementedDeviceState iomem0;
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UnimplementedDeviceState iomem1;
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UnimplementedDeviceState video;
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UnimplementedDeviceState emmc_boot_controller;
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UnimplementedDeviceState dpmcu;
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UnimplementedDeviceState pwm;
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UnimplementedDeviceState espi;
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UnimplementedDeviceState udc;
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UnimplementedDeviceState sgpiom;
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UnimplementedDeviceState ltpi;
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UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
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AspeedAPB2OPBState fsi[2];
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};
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#define TYPE_ASPEED_SOC "aspeed-soc"
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OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
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struct Aspeed2400SoCState {
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AspeedSoCState parent;
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ARMCPU cpu[ASPEED_CPUS_NUM];
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AspeedVICState vic;
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};
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#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
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struct Aspeed2600SoCState {
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AspeedSoCState parent;
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A15MPPrivState a7mpcore;
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ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
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};
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#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
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struct Aspeed27x0SoCState {
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AspeedSoCState parent;
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ARMCPU cpu[ASPEED_CPUS_NUM];
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AspeedINTCState intc[2];
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GICv3State gic;
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MemoryRegion dram_empty;
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};
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#define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
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struct Aspeed10x0SoCState {
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AspeedSoCState parent;
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ARMv7MState armv7m;
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};
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#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
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struct AspeedSoCClass {
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DeviceClass parent_class;
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/** valid_cpu_types: NULL terminated array of a single CPU type. */
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const char * const *valid_cpu_types;
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uint32_t silicon_rev;
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uint64_t sram_size;
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uint64_t secsram_size;
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int pcie_num;
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int spis_num;
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int ehcis_num;
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int wdts_num;
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int macs_num;
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int uarts_num;
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int uarts_base;
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const int *irqmap;
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const hwaddr *memmap;
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uint32_t num_cpus;
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bool (*boot_from_emmc)(AspeedSoCState *s);
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};
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enum {
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ASPEED_DEV_VBOOTROM,
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ASPEED_DEV_SPI_BOOT,
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ASPEED_DEV_IOMEM,
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ASPEED_DEV_IOMEM0,
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ASPEED_DEV_IOMEM1,
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ASPEED_DEV_LTPI,
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ASPEED_DEV_UART0,
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ASPEED_DEV_UART1,
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ASPEED_DEV_UART2,
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ASPEED_DEV_UART3,
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ASPEED_DEV_UART4,
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ASPEED_DEV_UART5,
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ASPEED_DEV_UART6,
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ASPEED_DEV_UART7,
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ASPEED_DEV_UART8,
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ASPEED_DEV_UART9,
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ASPEED_DEV_UART10,
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ASPEED_DEV_UART11,
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ASPEED_DEV_UART12,
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ASPEED_DEV_UART13,
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ASPEED_DEV_VUART,
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ASPEED_DEV_FMC,
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ASPEED_DEV_SPI0,
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ASPEED_DEV_SPI1,
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ASPEED_DEV_SPI2,
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ASPEED_DEV_EHCI1,
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ASPEED_DEV_EHCI2,
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ASPEED_DEV_EHCI3,
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ASPEED_DEV_EHCI4,
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ASPEED_DEV_VIC,
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ASPEED_DEV_INTC,
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ASPEED_DEV_INTCIO,
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ASPEED_DEV_SDMC,
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ASPEED_DEV_SCU,
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ASPEED_DEV_ADC,
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ASPEED_DEV_SBC,
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ASPEED_DEV_SECSRAM,
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ASPEED_DEV_EMMC_BC,
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ASPEED_DEV_VIDEO,
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ASPEED_DEV_SRAM,
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ASPEED_DEV_SDHCI,
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ASPEED_DEV_GPIO,
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ASPEED_DEV_GPIO_1_8V,
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ASPEED_DEV_RTC,
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ASPEED_DEV_TIMER1,
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ASPEED_DEV_TIMER2,
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ASPEED_DEV_TIMER3,
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ASPEED_DEV_TIMER4,
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ASPEED_DEV_TIMER5,
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ASPEED_DEV_TIMER6,
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ASPEED_DEV_TIMER7,
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ASPEED_DEV_TIMER8,
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ASPEED_DEV_WDT,
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ASPEED_DEV_PWM,
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ASPEED_DEV_LPC,
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ASPEED_DEV_IBT,
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ASPEED_DEV_I2C,
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ASPEED_DEV_PCIE0,
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ASPEED_DEV_PCIE1,
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ASPEED_DEV_PCIE2,
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ASPEED_DEV_PCIE_PHY0,
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ASPEED_DEV_PCIE_PHY1,
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ASPEED_DEV_PCIE_PHY2,
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ASPEED_DEV_PCIE_MMIO0,
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ASPEED_DEV_PCIE_MMIO1,
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ASPEED_DEV_PCIE_MMIO2,
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ASPEED_DEV_PECI,
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ASPEED_DEV_ETH1,
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ASPEED_DEV_ETH2,
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ASPEED_DEV_ETH3,
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ASPEED_DEV_ETH4,
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ASPEED_DEV_MII1,
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ASPEED_DEV_MII2,
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ASPEED_DEV_MII3,
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ASPEED_DEV_MII4,
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ASPEED_DEV_SDRAM,
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ASPEED_DEV_XDMA,
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ASPEED_DEV_EMMC,
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ASPEED_DEV_KCS,
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ASPEED_DEV_HACE,
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ASPEED_DEV_DPMCU,
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ASPEED_DEV_DP,
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ASPEED_DEV_I3C,
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ASPEED_DEV_ESPI,
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ASPEED_DEV_UDC,
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ASPEED_DEV_SGPIOM,
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ASPEED_DEV_JTAG0,
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ASPEED_DEV_JTAG1,
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ASPEED_DEV_FSI1,
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ASPEED_DEV_FSI2,
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ASPEED_DEV_SCUIO,
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ASPEED_DEV_SLI,
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ASPEED_DEV_SLIIO,
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ASPEED_GIC_DIST,
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ASPEED_GIC_REDIST,
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ASPEED_DEV_IPC0,
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ASPEED_DEV_IPC1,
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};
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const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
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bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
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const hwaddr addr, Error **errp);
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void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
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int uarts_num, Chardev *chr);
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bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
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void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
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hwaddr addr);
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void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev,
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const char *name, hwaddr addr,
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uint64_t size);
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void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
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unsigned int count, int unit0);
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void aspeed_write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
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Error **errp);
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void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
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MemoryRegion *boot_rom, uint64_t rom_size);
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void aspeed_load_vbootrom(AspeedSoCState *soc, const char *bios_name,
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Error **errp);
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static inline int aspeed_uart_index(int uart_dev)
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{
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return uart_dev - ASPEED_DEV_UART0;
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}
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static inline int aspeed_uart_first(int uarts_base)
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{
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return aspeed_uart_index(uarts_base);
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}
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static inline int aspeed_uart_last(int uarts_base, int uarts_num)
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{
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return aspeed_uart_first(uarts_base) + uarts_num - 1;
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}
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#endif /* ASPEED_SOC_H */
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