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Jamin LinandCédric Le Goater
10e377246d
In the original model, each subsystem (PSP, SSP, and TSP) created its own
set of 13 UART devices, resulting in a total of 39 UART instances. However,
on real AST2700 hardware, there is only one set of 13 UARTs shared among
all processors.
This commit reworks the UART handling to correctly model the shared
hardware design. The PSP now creates the full set of 13 UART instances,
while the SSP and TSP link to the corresponding shared UART device
through object properties.
Changes include:
- Add "DEFINE_PROP_LINK("uart", ...)" and "DEFINE_PROP_INT32("uart-dev", ...)"
to allow each coprocessor to reference a specific shared UART instance.
- Modify SSP to link to PSP’s UART4, and TSP to link to PSP’s UART7.
- Introduce "uart_alias" to remap the UART’s MMIO region into the coprocessor’s
memory space.
- Redirect the UART interrupt to the coprocessor’s NVIC, replacing the
default routing to the PSP’s GIC.
With this change, only one set of 13 UART devices is instantiated by the PSP,
while the SSP and TSP reuse them via aliasing and shared interrupt routing,
matching the real AST2700 hardware behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
/*
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* ASPEED Coprocessor
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*
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* Copyright (C) 2025 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_COPROCESSOR_H
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#define ASPEED_COPROCESSOR_H
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#include "qom/object.h"
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#include "hw/arm/aspeed_soc.h"
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struct AspeedCoprocessorState {
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DeviceState parent;
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MemoryRegion *memory;
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MemoryRegion sdram;
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MemoryRegion *sram;
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MemoryRegion sram_alias;
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MemoryRegion uart_alias;
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MemoryRegion scu_alias;
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Clock *sysclk;
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AspeedSCUState *scu;
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AspeedSCUState scuio;
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AspeedTimerCtrlState timerctrl;
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SerialMM *uart;
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int uart_dev;
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};
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#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
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OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
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ASPEED_COPROCESSOR)
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struct AspeedCoprocessorClass {
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DeviceClass parent_class;
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/** valid_cpu_types: NULL terminated array of a single CPU type. */
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const char * const *valid_cpu_types;
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const hwaddr *memmap;
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const int *irqmap;
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};
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struct Aspeed27x0CoprocessorState {
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AspeedCoprocessorState parent;
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AspeedINTCState intc[2];
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UnimplementedDeviceState ipc[2];
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UnimplementedDeviceState scuio;
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ARMv7MState armv7m;
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};
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#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
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OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState,
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ASPEED27X0SSP_COPROCESSOR)
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#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor"
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DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass,
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ASPEED27X0TSP_COPROCESSOR, TYPE_ASPEED27X0TSP_COPROCESSOR)
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#endif /* ASPEED_COPROCESSOR_H */
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