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2ee80bce4f7cf2ef78f996ea608755d4e97c94de
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53 Commits
Author SHA1 Message Date
Helge DellerandRichard Henderson 3bdf20819e target/hppa: Add diag instructions to set/restore shadow registers 
The 32-bit PA-7300LC (PCX-L2) CPU and the 64-bit PA8700 (PCX-W2) CPU
use different diag instructions to save or restore the CPU registers
to/from the shadow registers.

Implement those per-CPU architecture diag instructions to fix those
parts of the HP ODE testcases (L2DIAG and WDIAG, section 1) which test
the shadow registers.

Signed-off-by: Helge Deller <deller@gmx.de>
[rth: Use decodetree to distinguish cases]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>
 2024-03-29 08:14:56 -10:00
Richard Henderson 381931275a target/hppa: Move diag argument handling to decodetree 
Split trans_diag into per-operation functions.

Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-03-29 07:51:42 -10:00
Richard Henderson 82d0c831ce target/hppa: Squash d for pa1.x during decode 
The cond_need_ext predicate was created while we still had a
32-bit compilation mode.  It now makes more sense to treat D
as an absolute indicator of a 64-bit operation.

Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-03-27 12:15:25 -10:00
Sven SchnelleandRichard Henderson ad1fdacd1b target/hppa: exit tb on flush cache instructions 
When the guest modifies the tb it is currently executing from,
it executes a fic instruction. Exit the tb on such instruction,
otherwise we might execute stale code.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20240319161921.487080-5-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-03-19 14:08:02 -10:00
Richard Henderson 46174e140d target/hppa: Fix assemble_12a insns for wide mode 
Tested-by: Helge Deller <deller@gmx.de>
Reported-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-03-19 13:33:39 -10:00
Richard Henderson 4768c28edd target/hppa: Fix assemble_11a insns for wide mode 
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Reported-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-03-19 13:33:39 -10:00
Richard Henderson 72bace2d13 target/hppa: Fix assemble_16 insns for wide mode 
Reported-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-03-19 13:33:39 -10:00
Helge DellerandRichard Henderson eb25d10f4d target/hppa: Add pa2.0 cpu local tlb flushes 
The previous decoding misnamed the bit it called "local".
Other than the name, the implementation was correct for pa1.x.
Rename this field to "tlbe".

PA2.0 adds (a real) local bit to PxTLB, and also adds a range
of pages to flush in GR[b].

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 4e7abdb120 target/hppa: Implement PERMH 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson c2a7ee3f9d target/hppa: Implement MIXH, MIXW 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 3bbb8e4832 target/hppa: Implement HSHLADD, HSHRADD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 151f309b98 target/hppa: Implement HSHL, HSHR 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 1b3cb7c874 target/hppa: Implement HAVG 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 10c9e58d5c target/hppa: Implement HSUB 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 0843563f3e target/hppa: Implement HADD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 8577f35479 target/hppa: Implement IDTLBT, IITLBT 
Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus.  Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 25460fc5a7 target/hppa: Implement STDBY 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson a8966ba70a target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson f7b775a9c0 target/hppa: Implement SHRPD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson bd792da354 target/hppa: Implement EXTRD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 72ae4f2b82 target/hppa: Implement DEPD, DEPDI 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 51416c4e41 target/hppa: Implement LDD, LDCD, LDDA, STD, STDA 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson c65c3ee16b target/hppa: Decode CMPIB double-word 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson e9efd4bcdc target/hppa: Decode d for cmpb instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson 84e224d422 target/hppa: Decode d for bb instructions 
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00