izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity
127,923 Commits 2 Branches 7 Tags
master
Commit Graph
63 Commits
Author SHA1 Message Date
Michael Tokarev bad5cfcd60 i386: spelling fixes 
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 2023-09-20 07:54:34 +03:00
Michael Tokarev e6a19a6477 ppc: spelling fixes 
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
 2023-09-20 07:54:34 +03:00
Stefan Hajnoczi d7754940d7 Merge tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu into staging 
*: Delete checks for old host definitions
tcg/loongarch64: Generate LSX instructions
fpu: Add conversions between bfloat16 and [u]int8
fpu: Handle m68k extended precision denormals properly
accel/tcg: Improve cputlb i/o organization
accel/tcg: Simplify tlb_plugin_lookup
accel/tcg: Remove false-negative halted assertion
tcg: Add gvec compare with immediate and scalar operand
tcg/aarch64: Emit BTI insns at jump landing pads

[Resolved conflict between CPUINFO_PMULL and CPUINFO_BTI.
--Stefan]

* tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu: (39 commits)
  tcg: Map code_gen_buffer with PROT_BTI
  tcg/aarch64: Emit BTI insns at jump landing pads
  util/cpuinfo-aarch64: Add CPUINFO_BTI
  tcg: Add tcg_out_tb_start backend hook
  fpu: Handle m68k extended precision denormals properly
  fpu: Add conversions between bfloat16 and [u]int8
  accel/tcg: Introduce do_st16_mmio_leN
  accel/tcg: Introduce do_ld16_mmio_beN
  accel/tcg: Merge io_writex into do_st_mmio_leN
  accel/tcg: Merge io_readx into do_ld_mmio_beN
  accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1
  accel/tcg: Merge cpu_transaction_failed into io_failed
  plugin: Simplify struct qemu_plugin_hwaddr
  accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed
  accel/tcg: Split out io_prepare and io_failed
  accel/tcg: Simplify tlb_plugin_lookup
  target/arm: Use tcg_gen_gvec_cmpi for compare vs 0
  tcg: Add gvec compare with immediate and scalar operand
  tcg/loongarch64: Implement 128-bit load & store
  tcg/loongarch64: Lower rotli_vec to vrotri
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2023-09-19 13:20:54 -04:00
Richard Henderson 095859e5d9 util/cpuinfo-aarch64: Add CPUINFO_BTI 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-09-16 14:57:16 +00:00
Richard Henderson 055c99015a host/include/aarch64: Implement clmul.h 
Detect PMULL in cpuinfo; implement the accel hook.

Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-09-15 13:57:00 +00:00
Richard Henderson d6493dbb46 host/include/i386: Implement clmul.h 
Detect PCLMUL in cpuinfo; implement the accel hook.

Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-09-15 13:57:00 +00:00
Richard Henderson 00f463b38a crypto: Add generic 64-bit carry-less multiply routine 
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-09-15 13:57:00 +00:00
Michael Tokarev 8b81968c1c other architectures: spelling fixes 
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 2023-07-25 17:14:07 +03:00
Michael Tokarev 673d821541 arm: spelling fixes 
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 2023-07-25 17:13:53 +03:00
Richard Henderson 57357322e4 host/include/ppc: Implement aes-round.h 
Detect CRYPTO in cpuinfo; implement the accel hooks.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 8d97f28e36 host/include/aarch64: Implement aes-round.h 
Detect AES in cpuinfo; implement the accel hooks.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson d6a2443696 host/include/i386: Implement aes-round.h 
Detect AES in cpuinfo; implement the accel hooks.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 28e91474ce crypto: Add aesdec_ISB_ISR_AK_IMC 
Add a primitive for InvSubBytes + InvShiftRows +
AddRoundKey + InvMixColumns.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 15ff15982a crypto: Add aesdec_ISB_ISR_IMC_AK 
Add a primitive for InvSubBytes + InvShiftRows +
InvMixColumns + AddRoundKey.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 7c58cb972e crypto: Add aesenc_SB_SR_MC_AK 
Add a primitive for SubBytes + ShiftRows + MixColumns + AddRoundKey.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 5b41deb310 crypto: Add aesdec_IMC 
Add a primitive for InvMixColumns.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 04e1f30eed crypto: Add aesenc_MC 
Add a primitive for MixColumns.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 192fa84986 crypto: Add aesdec_ISB_ISR_AK 
Add a primitive for InvSubBytes + InvShiftRows + AddRoundKey.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 6b0a96ce3a crypto: Add aesenc_SB_SR_AK 
Start adding infrastructure for accelerating guest AES.
Begin with a SubBytes + ShiftRows + AddRoundKey primitive.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 623d7e3551 util: Add cpuinfo-ppc.c 
Move the code from tcg/.  Fix a bug in that PPC_FEATURE2_ARCH_3_10
is actually spelled PPC_FEATURE2_ARCH_3_1.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-07-08 07:30:17 +01:00
Richard Henderson 8a2bd74787 host/include/x86_64: Use __m128i for "x" constraints 
The macOS catalina compiler produces an error for __int128_t
as the type for allocation with SSE inline asm constraint.
Create a new X86Int128Union type and use the vector type for
all SSE register inputs and outputs.

Tested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-06-20 10:01:30 +02:00
Richard Henderson dd906a37c7 accel/tcg: Add aarch64 store_atom_insert_al16 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-05-30 09:51:12 -07:00
Richard Henderson 129fe7cddb accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-05-30 09:51:12 -07:00
Richard Henderson a8bde8da47 accel/tcg: Add x86_64 load_atom_extract_al16_or_al8 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-05-30 09:51:11 -07:00
Richard Henderson b3f4144fa9 accel/tcg: Extract store_atom_insert_al16 to host header 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-05-30 09:51:11 -07:00