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hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation
Add a new AspeedCoprocessor class that defines the foundational structure for ASPEED coprocessor models. This class encapsulates a base DeviceState with links to system memory, clock, and peripheral components such as SCU, SCUIO, Timer Controller, and UARTs. Introduce the corresponding implementation file aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize() method, property registration, and QOM type registration. The class is marked as abstract and intended to serve as a common base for specific coprocessor variants (e.g. SSP/TSP subsystems). This establishes a reusable and extensible framework for modeling ASPEED coprocessor devices. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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committed by
Cédric Le Goater
parent
21b3898a69
commit
d183ef19a8
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/*
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* ASPEED Coprocessor
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*
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* Copyright (C) 2025 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ASPEED_COPROCESSOR_H
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#define ASPEED_COPROCESSOR_H
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#include "qom/object.h"
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#include "hw/arm/aspeed_soc.h"
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struct AspeedCoprocessorState {
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DeviceState parent;
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MemoryRegion *memory;
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MemoryRegion sram;
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Clock *sysclk;
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AspeedSCUState scu;
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AspeedSCUState scuio;
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AspeedTimerCtrlState timerctrl;
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SerialMM uart[ASPEED_UARTS_NUM];
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};
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#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
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OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
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ASPEED_COPROCESSOR)
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struct AspeedCoprocessorClass {
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DeviceClass parent_class;
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/** valid_cpu_types: NULL terminated array of a single CPU type. */
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const char * const *valid_cpu_types;
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uint32_t silicon_rev;
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const hwaddr *memmap;
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const int *irqmap;
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int uarts_base;
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int uarts_num;
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};
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#endif /* ASPEED_COPROCESSOR_H */
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