izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

target/ppc: remove 401/403 CPUs

Browse Source 
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211202191108.1291515-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater
2021-12-17 17:57:16 +01:00
parent 84835acbbf
commit c8f49e6b93
7 changed files with 4 additions and 608 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/ppc/cpu-models.c
-34
View File
@@ -67,40 +67,6 @@
POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
/* Embedded PowerPC */
/* PowerPC 401 family */
POWERPC_DEF("401", CPU_POWERPC_401, 401,
"Generic PowerPC 401")
/* PowerPC 401 cores */
POWERPC_DEF("401a1", CPU_POWERPC_401A1, 401,
"PowerPC 401A1")
POWERPC_DEF("401b2", CPU_POWERPC_401B2, 401x2,
"PowerPC 401B2")
POWERPC_DEF("401c2", CPU_POWERPC_401C2, 401x2,
"PowerPC 401C2")
POWERPC_DEF("401d2", CPU_POWERPC_401D2, 401x2,
"PowerPC 401D2")
POWERPC_DEF("401e2", CPU_POWERPC_401E2, 401x2,
"PowerPC 401E2")
POWERPC_DEF("401f2", CPU_POWERPC_401F2, 401x2,
"PowerPC 401F2")
/* XXX: to be checked */
POWERPC_DEF("401g2", CPU_POWERPC_401G2, 401x2,
"PowerPC 401G2")
/* PowerPC 401 microcontrollers */
POWERPC_DEF("iop480", CPU_POWERPC_IOP480, IOP480,
"IOP480 (401 microcontroller)")
POWERPC_DEF("cobra", CPU_POWERPC_COBRA, 401,
"IBM Processor for Network Resources")
/* PowerPC 403 family */
/* PowerPC 403 microcontrollers */
POWERPC_DEF("403ga", CPU_POWERPC_403GA, 403,
"PowerPC 403 GA")
POWERPC_DEF("403gb", CPU_POWERPC_403GB, 403,
"PowerPC 403 GB")
POWERPC_DEF("403gc", CPU_POWERPC_403GC, 403,
"PowerPC 403 GC")
POWERPC_DEF("403gcx", CPU_POWERPC_403GCX, 403GCX,
"PowerPC 403 GCX")
/* PowerPC 405 family */
/* PowerPC 405 cores */
POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405,
target/ppc/cpu-models.h
-19
View File
@@ -38,27 +38,8 @@ extern PowerPCCPUAlias ppc_cpu_aliases[];
/*****************************************************************************/
/* PVR definitions for most known PowerPC */
enum {
/* PowerPC 401 family */
/* Generic PowerPC 401 */
#define CPU_POWERPC_401 CPU_POWERPC_401G2
/* PowerPC 401 cores */
CPU_POWERPC_401A1 = 0x00210000,
CPU_POWERPC_401B2 = 0x00220000,
CPU_POWERPC_401C2 = 0x00230000,
CPU_POWERPC_401D2 = 0x00240000,
CPU_POWERPC_401E2 = 0x00250000,
CPU_POWERPC_401F2 = 0x00260000,
CPU_POWERPC_401G2 = 0x00270000,
/* PowerPC 401 microcontrolers */
#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
/* IBM Processor for Network Resources */
CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
/* PowerPC 403 family */
/* PowerPC 403 microcontrollers */
CPU_POWERPC_403GA = 0x00200011,
CPU_POWERPC_403GB = 0x00200100,
CPU_POWERPC_403GC = 0x00200200,
CPU_POWERPC_403GCX = 0x00201400,
/* PowerPC 405 family */
/* PowerPC 405 cores */
CPU_POWERPC_405D2 = 0x20010000,
target/ppc/cpu-qom.h
-4
View File
@@ -53,8 +53,6 @@ enum powerpc_mmu_t {
POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC 4xx MMU with software TLB and zones protections */
POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
/* PowerPC MMU in real mode only */
POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
@@ -149,8 +147,6 @@ enum powerpc_input_t {
PPC_FLAGS_INPUT_POWER7,
/* PowerPC POWER9 bus */
PPC_FLAGS_INPUT_POWER9,
/* PowerPC 401 bus */
PPC_FLAGS_INPUT_401,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
};
target/ppc/cpu_init.c
-512
View File
File diff suppressed because it is too large Load Diff
target/ppc/excp_helper.c
-1
View File
@@ -1434,7 +1434,6 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
env->spr[SPR_40x_DEAR] = vaddr;
break;
case POWERPC_MMU_BOOKE:
target/ppc/mmu_common.c
+4 -37
View File
@@ -1173,11 +1173,9 @@ void dump_mmu(CPUPPCState *env)
static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
MMUAccessType access_type)
{
int in_plb, ret;
ctx->raddr = eaddr;
ctx->prot = PAGE_READ | PAGE_EXEC;
ret = 0;
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_4xx:
@@ -1186,39 +1184,12 @@ static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
ctx->prot |= PAGE_WRITE;
break;
case POWERPC_MMU_SOFT_4xx_Z:
if (unlikely(msr_pe != 0)) {
/*
* 403 family add some particular protections, using
* PBL/PBU registers for accesses with no translation.
*/
in_plb =
/* Check PLB validity */
(env->pb[0] < env->pb[1] &&
/* and address in plb area */
eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
(env->pb[2] < env->pb[3] &&
eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
if (in_plb ^ msr_px) {
/* Access in protected area */
if (access_type == MMU_DATA_STORE) {
/* Access is not allowed */
ret = -2;
}
} else {
/* Read-write access is allowed */
ctx->prot |= PAGE_WRITE;
}
}
break;
default:
/* Caller's checks mean we should never get here for other models */
abort();
return -1;
g_assert_not_reached();
}
return ret;
return 0;
}
int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
@@ -1247,7 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
break;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
if (real_mode) {
ret = check_physical(env, ctx, eaddr, access_type);
} else {
@@ -1381,7 +1351,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
goto tlb_miss;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = eaddr;
@@ -1449,7 +1418,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
get_pteg_offset32(cpu, ctx.hash[1]);
break;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = eaddr;
@@ -1482,8 +1450,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
/* Access rights violation */
cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
if (env->mmu_model == POWERPC_MMU_SOFT_4xx
|| env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
env->spr[SPR_40x_DEAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_40x_ESR] |= 0x00800000;
target/ppc/mmu_helper.c
-1
View File
@@ -388,7 +388,6 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
ppc6xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
ppc4xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_REAL: