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target/i386: add core of new i386 decoder
The new decoder is based on three principles: - use mostly table-driven decoding, using tables derived as much as possible from the Intel manual. Centralizing the decode the operands makes it more homogeneous, for example all immediates are signed. All modrm handling is in one function, and can be shared between SSE and ALU instructions (including XMM<->GPR instructions). The SSE/AVX decoder will also not have duplicated code between the 0F, 0F38 and 0F3A tables. - keep the code as "non-branchy" as possible. Generally, the code for the new decoder is more verbose, but the control flow is simpler. Conditionals are not nested and have small bodies. All instruction groups are resolved even before operands are decoded, and code generation is separated as much as possible within small functions that only handle one instruction each. - keep address generation and (for ALU operands) memory loads and writeback as much in common code as possible. All ALU operations for example are implemented as T0=f(T0,T1). For non-ALU instructions, read-modify-write memory operations are rare, but registers do not have TCGv equivalents: therefore, the common logic sets up pointer temporaries with the operands, while load and writeback are handled by gvec or by helpers. These principles make future code review and extensibility simpler, at the cost of having a relatively large amount of code in the form of this patch. Even EVEX should not be _too_ hard to implement (it's just a crazy large amount of possibilities). This patch introduces the main decoder flow, and integrates the old decoder with the new one. The old decoder takes care of parsing prefixes and then optionally drops to the new one. The changes to the old decoder are minimal and allow it to be replaced incrementally with the new one. There is a debugging mechanism through a "LIMIT" environment variable. In user-mode emulation, the variable is the number of instructions decoded by the new decoder before permanently switching to the old one. In system emulation, the variable is the highest opcode that is decoded by the new decoder (this is less friendly, but it's the best that can be done without requiring deterministic execution). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
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@@ -0,0 +1,181 @@
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/*
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* Decode table flags, mostly based on Intel SDM.
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*
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* Copyright (c) 2022 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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typedef enum X86OpType {
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X86_TYPE_None,
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X86_TYPE_A, /* Implicit */
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X86_TYPE_B, /* VEX.vvvv selects a GPR */
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X86_TYPE_C, /* REG in the modrm byte selects a control register */
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X86_TYPE_D, /* REG in the modrm byte selects a debug register */
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X86_TYPE_E, /* ALU modrm operand */
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X86_TYPE_F, /* EFLAGS/RFLAGS */
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X86_TYPE_G, /* REG in the modrm byte selects a GPR */
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X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */
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X86_TYPE_I, /* Immediate */
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X86_TYPE_J, /* Relative offset for a jump */
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X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
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X86_TYPE_M, /* modrm byte selects a memory operand */
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X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */
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X86_TYPE_O, /* Absolute address encoded in the instruction */
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X86_TYPE_P, /* reg in the modrm byte selects an MMX register */
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X86_TYPE_Q, /* MMX modrm operand */
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X86_TYPE_R, /* R/M in the modrm byte selects a register */
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X86_TYPE_S, /* reg selects a segment register */
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X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */
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X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */
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X86_TYPE_W, /* XMM/YMM modrm operand */
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X86_TYPE_X, /* string source */
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X86_TYPE_Y, /* string destination */
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/* Custom */
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X86_TYPE_2op, /* 2-operand RMW instruction */
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X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
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X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
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X86_TYPE_1,
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X86_TYPE_2,
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X86_TYPE_3,
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X86_TYPE_4,
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X86_TYPE_5,
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X86_TYPE_6,
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X86_TYPE_7,
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X86_TYPE_ES, /* Hard-coded segment registers */
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X86_TYPE_CS,
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X86_TYPE_SS,
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X86_TYPE_DS,
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X86_TYPE_FS,
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X86_TYPE_GS,
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} X86OpType;
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typedef enum X86OpSize {
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X86_SIZE_None,
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X86_SIZE_a, /* BOUND operand */
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X86_SIZE_b, /* byte */
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X86_SIZE_d, /* 32-bit */
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X86_SIZE_dq, /* SSE/AVX 128-bit */
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X86_SIZE_p, /* Far pointer */
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X86_SIZE_pd, /* SSE/AVX packed double precision */
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X86_SIZE_pi, /* MMX */
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X86_SIZE_ps, /* SSE/AVX packed single precision */
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X86_SIZE_q, /* 64-bit */
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X86_SIZE_qq, /* AVX 256-bit */
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X86_SIZE_s, /* Descriptor */
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X86_SIZE_sd, /* SSE/AVX scalar double precision */
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X86_SIZE_ss, /* SSE/AVX scalar single precision */
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X86_SIZE_si, /* 32-bit GPR */
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X86_SIZE_v, /* 16/32/64-bit, based on operand size */
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X86_SIZE_w, /* 16-bit */
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X86_SIZE_x, /* 128/256-bit, based on operand size */
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X86_SIZE_y, /* 32/64-bit, based on operand size */
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X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */
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/* Custom */
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X86_SIZE_d64,
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X86_SIZE_f64,
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} X86OpSize;
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/* Execution flags */
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typedef enum X86OpUnit {
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X86_OP_SKIP, /* not valid or managed by emission function */
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X86_OP_SEG, /* segment selector */
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X86_OP_CR, /* control register */
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X86_OP_DR, /* debug register */
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X86_OP_INT, /* loaded into/stored from s->T0/T1 */
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X86_OP_IMM, /* immediate */
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X86_OP_SSE, /* address in either s->ptrX or s->A0 depending on has_ea */
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X86_OP_MMX, /* address in either s->ptrX or s->A0 depending on has_ea */
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} X86OpUnit;
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typedef enum X86InsnSpecial {
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X86_SPECIAL_None,
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/* Always locked if it has a memory operand (XCHG) */
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X86_SPECIAL_Locked,
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/* Fault outside protected mode */
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X86_SPECIAL_ProtMode,
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/*
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* Register operand 0/2 is zero extended to 32 bits. Rd/Mb or Rd/Mw
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* in the manual.
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*/
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X86_SPECIAL_ZExtOp0,
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X86_SPECIAL_ZExtOp2,
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/*
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* MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands
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* become P/P/Q/N, and size "x" becomes "q".
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*/
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X86_SPECIAL_MMX,
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/* Illegal or exclusive to 64-bit mode */
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X86_SPECIAL_i64,
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X86_SPECIAL_o64,
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} X86InsnSpecial;
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typedef struct X86OpEntry X86OpEntry;
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typedef struct X86DecodedInsn X86DecodedInsn;
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/* Decode function for multibyte opcodes. */
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typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b);
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/* Code generation function. */
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typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode);
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struct X86OpEntry {
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/* Based on the is_decode flags. */
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union {
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X86GenFunc gen;
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X86DecodeFunc decode;
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};
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/* op0 is always written, op1 and op2 are always read. */
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X86OpType op0:8;
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X86OpSize s0:8;
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X86OpType op1:8;
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X86OpSize s1:8;
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X86OpType op2:8;
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X86OpSize s2:8;
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/* Must be I and b respectively if present. */
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X86OpType op3:8;
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X86OpSize s3:8;
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X86InsnSpecial special:8;
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bool is_decode:1;
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};
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typedef struct X86DecodedOp {
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int8_t n;
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MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */
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X86OpUnit unit;
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bool has_ea;
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} X86DecodedOp;
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struct X86DecodedInsn {
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X86OpEntry e;
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X86DecodedOp op[3];
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target_ulong immediate;
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AddressParts mem;
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uint8_t b;
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};
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@@ -0,0 +1,31 @@
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/*
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* New-style TCG opcode generator for i386 instructions
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*
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* Copyright (c) 2022 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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static void gen_illegal(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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{
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gen_illegal_opcode(s);
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}
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static void gen_load_ea(DisasContext *s, AddressParts *mem)
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{
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TCGv ea = gen_lea_modrm_1(s, *mem);
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gen_lea_v_seg(s, s->aflag, ea, mem->def_seg, s->override);
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}
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@@ -86,6 +86,9 @@ typedef struct DisasContext {
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int8_t override; /* -1 if no override, else R_CS, R_DS, etc */
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uint8_t prefix;
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bool has_modrm;
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uint8_t modrm;
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#ifndef CONFIG_USER_ONLY
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uint8_t cpl; /* code priv level */
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uint8_t iopl; /* i/o priv level */
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@@ -2425,6 +2428,31 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)
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return ret;
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}
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static target_long insn_get_signed(CPUX86State *env, DisasContext *s, MemOp ot)
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{
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target_long ret;
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switch (ot) {
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case MO_8:
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ret = (int8_t) x86_ldub_code(env, s);
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break;
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case MO_16:
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ret = (int16_t) x86_lduw_code(env, s);
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break;
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case MO_32:
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ret = (int32_t) x86_ldl_code(env, s);
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break;
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#ifdef TARGET_X86_64
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case MO_64:
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ret = x86_ldq_code(env, s);
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break;
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#endif
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default:
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g_assert_not_reached();
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}
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return ret;
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}
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static inline int insn_const_size(MemOp ot)
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{
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if (ot <= MO_32) {
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@@ -2927,6 +2955,11 @@ typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
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typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
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TCGv val);
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static bool first = true; static unsigned long limit;
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#include "decode-new.h"
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#include "emit.c.inc"
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#include "decode-new.c.inc"
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#define SSE_OPF_CMP (1 << 1) /* does not write for first operand */
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#define SSE_OPF_SPECIAL (1 << 3) /* magic */
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#define SSE_OPF_3DNOW (1 << 4) /* 3DNow! instruction */
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@@ -4859,10 +4892,35 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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prefixes = 0;
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if (first) first = false, limit = getenv("LIMIT") ? atol(getenv("LIMIT")) : -1;
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bool use_new = true;
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#ifdef CONFIG_USER_ONLY
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use_new &= limit > 0;
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#endif
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next_byte:
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s->prefix = prefixes;
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b = x86_ldub_code(env, s);
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/* Collect prefixes. */
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switch (b) {
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default:
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#ifndef CONFIG_USER_ONLY
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use_new &= b <= limit;
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#endif
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if (use_new && 0) {
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disas_insn_new(s, cpu, b);
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return s->pc;
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}
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break;
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case 0x0f:
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b = x86_ldub_code(env, s) + 0x100;
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#ifndef CONFIG_USER_ONLY
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use_new &= b <= limit;
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#endif
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if (use_new && 0) {
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disas_insn_new(s, cpu, b + 0x100);
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return s->pc;
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}
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break;
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case 0xf3:
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prefixes |= PREFIX_REPZ;
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prefixes &= ~PREFIX_REPNZ;
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@@ -4913,6 +4971,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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#endif
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case 0xc5: /* 2-byte VEX */
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case 0xc4: /* 3-byte VEX */
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use_new = false;
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/* VEX prefixes cannot be used except in 32-bit mode.
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Otherwise the instruction is LES or LDS. */
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if (CODE32(s) && !VM86(s)) {
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@@ -4997,14 +5056,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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s->dflag = dflag;
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/* now check op code */
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reswitch:
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switch(b) {
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case 0x0f:
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/**************************/
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/* extended op code */
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b = x86_ldub_code(env, s) | 0x100;
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goto reswitch;
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switch (b) {
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/**************************/
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/* arith & logic */
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case 0x00 ... 0x05:
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