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Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4920 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
2008-07-21 20:40:22 +00:00
parent 51fec3cc7e
commit afbb5194d4
7 changed files with 900 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Makefile.target
+1 -1
View File
@@ -594,7 +594,7 @@ OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
OBJS+= pflash_cfi01.o gumstix.o
OBJS+= zaurus.o ide.o serial.o nand.o ecc.o spitz.o tosa.o tc6393xb.o
OBJS+= omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
OBJS+= omap2.o omap_dss.o
OBJS+= omap2.o omap_dss.o soc_dma.o
OBJS+= palm.o tsc210x.o
OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
OBJS+= tsc2005.o
hw/omap.h
+6 -6
View File
@@ -417,14 +417,14 @@ enum omap_dma_model {
omap_dma_4,
};
struct omap_dma_s;
struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s;
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
void omap_dma_reset(struct omap_dma_s *s);
void omap_dma_reset(struct soc_dma_s *s);
struct dma_irq_map {
int ih;
@@ -494,7 +494,7 @@ struct omap_dma_lcd_channel_s {
ram_addr_t phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct omap_dma_s *s);
} *omap_dma_get_lcdch(struct soc_dma_s *s);
/*
* DMA request numbers for OMAP1
@@ -882,7 +882,7 @@ struct omap_mpu_state_s {
/* MPU private TIPB peripherals */
struct omap_intr_handler_s *ih[2];
struct omap_dma_s *dma;
struct soc_dma_s *dma;
struct omap_mpu_timer_s *timer[3];
struct omap_watchdog_timer_s *wdt;
hw/omap1.c
+7
View File
@@ -24,6 +24,7 @@
#include "sysemu.h"
#include "qemu-timer.h"
#include "qemu-char.h"
#include "soc_dma.h"
/* We use pc-style serial ports. */
#include "pc.h"
@@ -4704,6 +4705,12 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
s->port[local ].addr_valid = omap_validate_local_addr;
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
/* Register SDRAM and SRAM DMA ports for fast transfers. */
soc_dma_port_add_mem_ram(s->dma,
emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
soc_dma_port_add_mem_ram(s->dma,
imif_base, OMAP_IMIF_BASE, s->sram_size);
s->timer[0] = omap_mpu_timer_init(0xfffec500,
s->irq[0][OMAP_INT_TIMER1],
omap_findclk(s, "mputim_ck"));
hw/omap2.c
+5
View File
@@ -26,6 +26,7 @@
#include "qemu-timer.h"
#include "qemu-char.h"
#include "flash.h"
#include "soc_dma.h"
#include "audio/audio.h"
/* GP timers */
@@ -4493,6 +4494,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_findclk(s, "sdma_fclk"));
s->port->addr_valid = omap2_validate_addr;
/* Register SDRAM and SRAM ports for fast DMA transfers. */
soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
s->irq[0][OMAP_INT_24XX_UART1_IRQ],
omap_findclk(s, "uart1_fclk"),
hw/omap_dma.c
+400 -161
View File
File diff suppressed because it is too large Load Diff
hw/soc_dma.c
+366
View File
@@ -0,0 +1,366 @@
/*
* On-chip DMA controller framework.
*
* Copyright (C) 2008 Nokia Corporation
* Written by Andrzej Zaborowski <andrew@openedhand.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "qemu-common.h"
#include "qemu-timer.h"
#include "soc_dma.h"
void transfer_mem2mem(struct soc_dma_ch_s *ch)
{
memcpy(ch->paddr[0], ch->paddr[1], ch->bytes);
ch->paddr[0] += ch->bytes;
ch->paddr[1] += ch->bytes;
}
void transfer_mem2fifo(struct soc_dma_ch_s *ch)
{
ch->io_fn[1](ch->io_opaque[1], ch->paddr[0], ch->bytes);
ch->paddr[0] += ch->bytes;
}
void transfer_fifo2mem(struct soc_dma_ch_s *ch)
{
ch->io_fn[0](ch->io_opaque[0], ch->paddr[1], ch->bytes);
ch->paddr[1] += ch->bytes;
}
/* This is further optimisable but isn't very important because often
* DMA peripherals forbid this kind of transfers and even when they don't,
* oprating systems may not need to use them. */
static void *fifo_buf;
static int fifo_size;
void transfer_fifo2fifo(struct soc_dma_ch_s *ch)
{
if (ch->bytes < fifo_size)
fifo_buf = realloc(fifo_buf, fifo_size = ch->bytes);
/* Implement as transfer_fifo2linear + transfer_linear2fifo. */
ch->io_fn[0](ch->io_opaque[0], fifo_buf, ch->bytes);
ch->io_fn[1](ch->io_opaque[1], fifo_buf, ch->bytes);
}
struct dma_s {
struct soc_dma_s soc;
int chnum;
uint64_t ch_enable_mask;
int64_t channel_freq;
int enabled_count;
struct memmap_entry_s {
enum soc_dma_port_type type;
target_phys_addr_t addr;
union {
struct {
void *opaque;
soc_dma_io_t fn;
int out;
} fifo;
struct {
void *base;
size_t size;
} mem;
} u;
} *memmap;
int memmap_size;
struct soc_dma_ch_s ch[0];
};
static void soc_dma_ch_schedule(struct soc_dma_ch_s *ch, int delay_bytes)
{
int64_t now = qemu_get_clock(vm_clock);
struct dma_s *dma = (struct dma_s *) ch->dma;
qemu_mod_timer(ch->timer, now + delay_bytes / dma->channel_freq);
}
static void soc_dma_ch_run(void *opaque)
{
struct soc_dma_ch_s *ch = (struct soc_dma_ch_s *) opaque;
ch->running = 1;
ch->dma->setup_fn(ch);
ch->transfer_fn(ch);
ch->running = 0;
if (ch->enable)
soc_dma_ch_schedule(ch, ch->bytes);
ch->bytes = 0;
}
static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma,
target_phys_addr_t addr)
{
struct memmap_entry_s *lo;
int hi;
lo = dma->memmap;
hi = dma->memmap_size;
while (hi > 1) {
hi /= 2;
if (lo[hi].addr <= addr)
lo += hi;
}
return lo;
}
static inline enum soc_dma_port_type soc_dma_ch_update_type(
struct soc_dma_ch_s *ch, int port)
{
struct dma_s *dma = (struct dma_s *) ch->dma;
struct memmap_entry_s *entry = soc_dma_lookup(dma, ch->vaddr[port]);
if (entry->type == soc_dma_port_fifo) {
while (entry < dma->memmap + dma->memmap_size &&
entry->u.fifo.out != port)
entry ++;
if (entry->addr != ch->vaddr[port] || entry->u.fifo.out != port)
return soc_dma_port_other;
if (ch->type[port] != soc_dma_access_const)
return soc_dma_port_other;
ch->io_fn[port] = entry->u.fifo.fn;
ch->io_opaque[port] = entry->u.fifo.opaque;
return soc_dma_port_fifo;
} else if (entry->type == soc_dma_port_mem) {
if (entry->addr > ch->vaddr[port] ||
entry->addr + entry->u.mem.size <= ch->vaddr[port])
return soc_dma_port_other;
/* TODO: support constant memory address for source port as used for
* drawing solid rectangles by PalmOS(R). */
if (ch->type[port] != soc_dma_access_const)
return soc_dma_port_other;
ch->paddr[port] = (uint8_t *) entry->u.mem.base +
(ch->vaddr[port] - entry->addr);
/* TODO: save bytes left to the end of the mapping somewhere so we
* can check we're not reading beyond it. */
return soc_dma_port_mem;
} else
return soc_dma_port_other;
}
void soc_dma_ch_update(struct soc_dma_ch_s *ch)
{
enum soc_dma_port_type src, dst;
src = soc_dma_ch_update_type(ch, 0);
if (src == soc_dma_port_other) {
ch->update = 0;
ch->transfer_fn = ch->dma->transfer_fn;
return;
}
dst = soc_dma_ch_update_type(ch, 1);
/* TODO: use src and dst as array indices. */
if (src == soc_dma_port_mem && dst == soc_dma_port_mem)
ch->transfer_fn = transfer_mem2mem;
else if (src == soc_dma_port_mem && dst == soc_dma_port_fifo)
ch->transfer_fn = transfer_mem2fifo;
else if (src == soc_dma_port_fifo && dst == soc_dma_port_mem)
ch->transfer_fn = transfer_fifo2mem;
else if (src == soc_dma_port_fifo && dst == soc_dma_port_fifo)
ch->transfer_fn = transfer_fifo2fifo;
else
ch->transfer_fn = ch->dma->transfer_fn;
ch->update = (dst != soc_dma_port_other);
}
static void soc_dma_ch_freq_update(struct dma_s *s)
{
if (s->enabled_count)
/* We completely ignore channel priorities and stuff */
s->channel_freq = s->soc.freq / s->enabled_count;
else
/* TODO: Signal that we want to disable the functional clock and let
* the platform code decide what to do with it, i.e. check that
* auto-idle is enabled in the clock controller and if we are stopping
* the clock, do the same with any parent clocks that had only one
* user keeping them on and auto-idle enabled. */;
}
void soc_dma_set_request(struct soc_dma_ch_s *ch, int level)
{
struct dma_s *dma = (struct dma_s *) ch->dma;
dma->enabled_count += level - ch->enable;
if (level)
dma->ch_enable_mask |= 1 << ch->num;
else
dma->ch_enable_mask &= ~(1 << ch->num);
if (level != ch->enable) {
soc_dma_ch_freq_update(dma);
ch->enable = level;
if (!ch->enable)
qemu_del_timer(ch->timer);
else if (!ch->running)
soc_dma_ch_run(ch);
else
soc_dma_ch_schedule(ch, 1);
}
}
void soc_dma_reset(struct soc_dma_s *soc)
{
struct dma_s *s = (struct dma_s *) soc;
s->soc.drqbmp = 0;
s->ch_enable_mask = 0;
s->enabled_count = 0;
soc_dma_ch_freq_update(s);
}
/* TODO: take a functional-clock argument */
struct soc_dma_s *soc_dma_init(int n)
{
int i;
struct dma_s *s = qemu_mallocz(sizeof(*s) + n * sizeof(*s->ch));
s->chnum = n;
s->soc.ch = s->ch;
for (i = 0; i < n; i ++) {
s->ch[i].dma = &s->soc;
s->ch[i].num = i;
s->ch[i].timer = qemu_new_timer(vm_clock, soc_dma_ch_run, &s->ch[i]);
}
soc_dma_reset(&s->soc);
return &s->soc;
}
void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base,
soc_dma_io_t fn, void *opaque, int out)
{
struct memmap_entry_s *entry;
struct dma_s *dma = (struct dma_s *) soc;
dma->memmap = realloc(dma->memmap, sizeof(*entry) *
(dma->memmap_size + 1));
entry = soc_dma_lookup(dma, virt_base);
if (dma->memmap_size) {
if (entry->type == soc_dma_port_mem) {
if (entry->addr <= virt_base &&
entry->addr + entry->u.mem.size > virt_base) {
fprintf(stderr, "%s: FIFO at " TARGET_FMT_lx
" collides with RAM region at " TARGET_FMT_lx
"-" TARGET_FMT_lx "\n", __FUNCTION__,
(target_ulong) virt_base,
(target_ulong) entry->addr, (target_ulong)
(entry->addr + entry->u.mem.size));
exit(-1);
}
if (entry->addr <= virt_base)
entry ++;
} else
while (entry < dma->memmap + dma->memmap_size &&
entry->addr <= virt_base) {
if (entry->addr == virt_base && entry->u.fifo.out == out) {
fprintf(stderr, "%s: FIFO at " TARGET_FMT_lx
" collides FIFO at " TARGET_FMT_lx "\n",
__FUNCTION__, (target_ulong) virt_base,
(target_ulong) entry->addr);
exit(-1);
}
entry ++;
}
memmove(entry + 1, entry,
(uint8_t *) (dma->memmap + dma->memmap_size ++) -
(uint8_t *) entry);
} else
dma->memmap_size ++;
entry->addr = virt_base;
entry->type = soc_dma_port_fifo;
entry->u.fifo.fn = fn;
entry->u.fifo.opaque = opaque;
entry->u.fifo.out = out;
}
void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
target_phys_addr_t virt_base, size_t size)
{
struct memmap_entry_s *entry;
struct dma_s *dma = (struct dma_s *) soc;
dma->memmap = realloc(dma->memmap, sizeof(*entry) *
(dma->memmap_size + 1));
entry = soc_dma_lookup(dma, virt_base);
if (dma->memmap_size) {
if (entry->type == soc_dma_port_mem) {
if ((entry->addr >= virt_base && entry->addr < virt_base + size) ||
(entry->addr <= virt_base &&
entry->addr + entry->u.mem.size > virt_base)) {
fprintf(stderr, "%s: RAM at " TARGET_FMT_lx "-" TARGET_FMT_lx
" collides with RAM region at " TARGET_FMT_lx
"-" TARGET_FMT_lx "\n", __FUNCTION__,
(target_ulong) virt_base,
(target_ulong) (virt_base + size),
(target_ulong) entry->addr, (target_ulong)
(entry->addr + entry->u.mem.size));
exit(-1);
}
if (entry->addr <= virt_base)
entry ++;
} else {
if (entry->addr >= virt_base &&
entry->addr < virt_base + size) {
fprintf(stderr, "%s: RAM at " TARGET_FMT_lx "-" TARGET_FMT_lx
" collides with FIFO at " TARGET_FMT_lx
"\n", __FUNCTION__,
(target_ulong) virt_base,
(target_ulong) (virt_base + size),
(target_ulong) entry->addr);
exit(-1);
}
while (entry < dma->memmap + dma->memmap_size &&
entry->addr <= virt_base)
entry ++;
}
memmove(entry + 1, entry,
(uint8_t *) (dma->memmap + dma->memmap_size ++) -
(uint8_t *) entry);
} else
dma->memmap_size ++;
entry->addr = virt_base;
entry->type = soc_dma_port_mem;
entry->u.mem.base = phys_base;
entry->u.mem.size = size;
}
/* TODO: port removal for ports like PCMCIA memory */
hw/soc_dma.h
+115
View File
@@ -0,0 +1,115 @@
/*
* On-chip DMA controller framework.
*
* Copyright (C) 2008 Nokia Corporation
* Written by Andrzej Zaborowski <andrew@openedhand.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
struct soc_dma_s;
struct soc_dma_ch_s;
typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch);
enum soc_dma_port_type {
soc_dma_port_mem,
soc_dma_port_fifo,
soc_dma_port_other,
};
enum soc_dma_access_type {
soc_dma_access_const,
soc_dma_access_linear,
soc_dma_access_other,
};
struct soc_dma_ch_s {
/* Private */
struct soc_dma_s *dma;
int num;
QEMUTimer *timer;
/* Set by soc_dma.c */
int enable;
int update;
/* This should be set by dma->setup_fn(). */
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
void *io_opaque[2];
int running;
soc_dma_transfer_t transfer_fn;
/* Set and used by the DMA module. */
void *opaque;
};
struct soc_dma_s {
/* Following fields are set by the SoC DMA module and can be used
* by anybody. */
uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
qemu_irq *drq;
void *opaque;
int64_t freq;
soc_dma_transfer_t transfer_fn;
soc_dma_transfer_t setup_fn;
/* Set by soc_dma_init() for use by the DMA module. */
struct soc_dma_ch_s *ch;
};
/* Call to activate or stop a DMA channel. */
void soc_dma_set_request(struct soc_dma_ch_s *ch, int level);
/* Call after every write to one of the following fields and before
* calling soc_dma_set_request(ch, 1):
* ch->type[0...1],
* ch->vaddr[0...1],
* ch->paddr[0...1],
* or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */
void soc_dma_ch_update(struct soc_dma_ch_s *ch);
/* The SoC should call this when the DMA module is being reset. */
void soc_dma_reset(struct soc_dma_s *s);
struct soc_dma_s *soc_dma_init(int n);
void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
soc_dma_io_t fn, void *opaque, int out);
void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
target_phys_addr_t virt_base, size_t size);
static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
}
static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
}
static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma,
ram_addr_t offset, target_phys_addr_t virt_base, size_t size)
{
return soc_dma_port_add_mem(dma, phys_ram_base + offset, virt_base, size);
}