From a5844ea5530b664ea70852418fb751d63c15dba5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 24 Jan 2025 18:43:36 +0100 Subject: [PATCH 01/24] hw/char/sh_serial: Delete fifo_timeout_timer in DeviceUnrealize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fifo_timeout_timer is created in the DeviceRealize handler, not in the instance_init one. For parity, delete it in DeviceUnrealize, rather than instance_finalize. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-Id: <20250124175053.74461-2-philmd@linaro.org> --- hw/char/sh_serial.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 6abd80386f..cdaeac7b70 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -434,9 +434,9 @@ static void sh_serial_realize(DeviceState *d, Error **errp) s->etu = NANOSECONDS_PER_SECOND / 9600; } -static void sh_serial_finalize(Object *obj) +static void sh_serial_unrealize(DeviceState *dev) { - SHSerialState *s = SH_SERIAL(obj); + SHSerialState *s = SH_SERIAL(dev); timer_del(&s->fifo_timeout_timer); } @@ -445,6 +445,10 @@ static void sh_serial_init(Object *obj) { } +static void sh_serial_finalize(Object *obj) +{ +} + static const Property sh_serial_properties[] = { DEFINE_PROP_CHR("chardev", SHSerialState, chr), DEFINE_PROP_UINT8("features", SHSerialState, feat, 0), @@ -456,6 +460,7 @@ static void sh_serial_class_init(ObjectClass *oc, const void *data) device_class_set_props(dc, sh_serial_properties); dc->realize = sh_serial_realize; + dc->unrealize = sh_serial_unrealize; device_class_set_legacy_reset(dc, sh_serial_reset); /* Reason: part of SuperH CPU/SoC, needs to be wired up */ dc->user_creatable = false; From 65561d9393cfa21eb696bb759122641a569de63a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 24 Jan 2025 18:46:27 +0100 Subject: [PATCH 02/24] hw/char/sh_serial: Convert to TypeInfo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QOM types are now registered using as TypeInfo via DEFINE_TYPES() or type_init(). Update TYPE_SH_SERIAL, removing the empty QOM instance_init/finalize handlers. This was definitely wrong, because OBJECT_DEFINE_TYPE() is only for cases where the class needs its own virtual methods or some other per-class state in its own class struct. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-Id: <20250124175053.74461-3-philmd@linaro.org> --- hw/char/sh_serial.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index cdaeac7b70..30447fa018 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -78,10 +78,6 @@ struct SHSerialState { qemu_irq bri; }; -typedef struct {} SHSerialStateClass; - -OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE) - static void sh_serial_clear_fifo(SHSerialState *s) { memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); @@ -441,14 +437,6 @@ static void sh_serial_unrealize(DeviceState *dev) timer_del(&s->fifo_timeout_timer); } -static void sh_serial_init(Object *obj) -{ -} - -static void sh_serial_finalize(Object *obj) -{ -} - static const Property sh_serial_properties[] = { DEFINE_PROP_CHR("chardev", SHSerialState, chr), DEFINE_PROP_UINT8("features", SHSerialState, feat, 0), @@ -465,3 +453,14 @@ static void sh_serial_class_init(ObjectClass *oc, const void *data) /* Reason: part of SuperH CPU/SoC, needs to be wired up */ dc->user_creatable = false; } + +static const TypeInfo sh_serial_types[] = { + { + .name = TYPE_SH_SERIAL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SHSerialState), + .class_init = sh_serial_class_init, + }, +}; + +DEFINE_TYPES(sh_serial_types) From 8a486e3902177b1d0faaed6f372909767a019124 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sun, 4 May 2025 18:01:27 +0200 Subject: [PATCH 03/24] hw/pci-host/raven: Remove is-legacy-prep property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was a workaround for the prep machine that was removed 5 years ago so this is no longer needed. Fixes: b2ce76a073 (hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS) Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <0d41c18a8831bd4c8b0948eda3ef8f60f5a311f3.1746374076.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/raven.c | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index 21f7ca65e0..b78a8f32d3 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -75,7 +75,6 @@ struct PRePPCIState { RavenPCIState pci_dev; int contiguous_map; - bool is_legacy_prep; }; #define BIOS_SIZE (1 * MiB) @@ -243,22 +242,18 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) MemoryRegion *address_space_mem = get_system_memory(); int i; - if (s->is_legacy_prep) { - for (i = 0; i < PCI_NUM_PINS; i++) { - sysbus_init_irq(dev, &s->pci_irqs[i]); - } - } else { - /* According to PReP specification section 6.1.6 "System Interrupt - * Assignments", all PCI interrupts are routed via IRQ 15 */ - s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); - object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS, - &error_fatal); - qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); - sysbus_init_irq(dev, &s->or_irq->out_irq); + /* + * According to PReP specification section 6.1.6 "System Interrupt + * Assignments", all PCI interrupts are routed via IRQ 15 + */ + s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); + object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS, + &error_fatal); + qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); + sysbus_init_irq(dev, &s->or_irq->out_irq); - for (i = 0; i < PCI_NUM_PINS; i++) { - s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); - } + for (i = 0; i < PCI_NUM_PINS; i++) { + s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); } qdev_init_gpio_in(d, raven_change_gpio, 1); @@ -426,9 +421,6 @@ static const Property raven_pcihost_properties[] = { DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, EM_NONE), DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), - /* Temporary workaround until legacy prep machine is removed */ - DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep, - false), }; static void raven_pcihost_class_init(ObjectClass *klass, const void *data) From 63151361fdf14e9dcaa463fe06e0b23f51c689eb Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sun, 4 May 2025 18:01:28 +0200 Subject: [PATCH 04/24] hw/pci-host/raven: Revert "raven: Move BIOS loading from board code to PCI host" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit d0b25425749d5525b2ba6d9d966d8800a5643b35. Loading firmware from the PCI host is unusual and raven is only used by one board so this does not simplify anything but rather complicates it. Revert to loading firmware from board code as that is the usual way and also because raven has nothing to do with ROM so it is not a good place for this. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <4ca4f71bf661923d9a91b7e6776a0e40726e2337.1746374076.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/raven.c | 55 --------------------------------------------- hw/ppc/prep.c | 27 ++++++++++++++++++++-- 2 files changed, 25 insertions(+), 57 deletions(-) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index b78a8f32d3..f8c0be5d21 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -24,7 +24,6 @@ */ #include "qemu/osdep.h" -#include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/log.h" #include "qapi/error.h" @@ -35,9 +34,7 @@ #include "migration/vmstate.h" #include "hw/intc/i8259.h" #include "hw/irq.h" -#include "hw/loader.h" #include "hw/or-irq.h" -#include "elf.h" #include "qom/object.h" #define TYPE_RAVEN_PCI_DEVICE "raven" @@ -47,10 +44,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE) struct RavenPCIState { PCIDevice dev; - - uint32_t elf_machine; - char *bios_name; - MemoryRegion bios; }; typedef struct PRePPCIState PREPPCIState; @@ -77,8 +70,6 @@ struct PRePPCIState { int contiguous_map; }; -#define BIOS_SIZE (1 * MiB) - #define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */ static inline uint32_t raven_pci_io_config(hwaddr addr) @@ -333,48 +324,9 @@ static void raven_pcihost_initfn(Object *obj) static void raven_realize(PCIDevice *d, Error **errp) { - RavenPCIState *s = RAVEN_PCI_DEVICE(d); - char *filename; - int bios_size = -1; - d->config[PCI_CACHE_LINE_SIZE] = 0x08; d->config[PCI_LATENCY_TIMER] = 0x10; d->config[PCI_CAPABILITY_LIST] = 0x00; - - if (!memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", - BIOS_SIZE, errp)) { - return; - } - memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), - &s->bios); - if (s->bios_name) { - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); - if (filename) { - if (s->elf_machine != EM_NONE) { - bios_size = load_elf(filename, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, - ELFDATA2MSB, s->elf_machine, 0, 0); - } - if (bios_size < 0) { - bios_size = get_image_size(filename); - if (bios_size > 0 && bios_size <= BIOS_SIZE) { - hwaddr bios_addr; - bios_size = (bios_size + 0xfff) & ~0xfff; - bios_addr = (uint32_t)(-BIOS_SIZE); - bios_size = load_image_targphys(filename, bios_addr, - bios_size); - } - } - } - g_free(filename); - if (bios_size < 0 || bios_size > BIOS_SIZE) { - memory_region_del_subregion(get_system_memory(), &s->bios); - error_setg(errp, "Could not load bios image '%s'", s->bios_name); - return; - } - } - - vmstate_register_ram_global(&s->bios); } static const VMStateDescription vmstate_raven = { @@ -417,19 +369,12 @@ static const TypeInfo raven_info = { }, }; -static const Property raven_pcihost_properties[] = { - DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, - EM_NONE), - DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), -}; - static void raven_pcihost_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->realize = raven_pcihost_realizefn; - device_class_set_props(dc, raven_pcihost_properties); dc->fw_name = "pci"; } diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 739526335c..982e40e53e 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -35,6 +35,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/log.h" +#include "qemu/datadir.h" #include "hw/loader.h" #include "hw/rtc/mc146818rtc.h" #include "hw/isa/pc87312.h" @@ -55,6 +56,8 @@ #define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 +#define BIOS_ADDR 0xfff00000 +#define BIOS_SIZE (1 * MiB) #define NVRAM_SIZE 0x2000 static void fw_cfg_boot_set(void *opaque, const char *boot_device, @@ -241,6 +244,9 @@ static void ibm_40p_init(MachineState *machine) ISADevice *isa_dev; ISABus *isa_bus; void *fw_cfg; + MemoryRegion *bios = g_new(MemoryRegion, 1); + char *filename; + ssize_t bios_size = -1; uint32_t kernel_base = 0, initrd_base = 0; long kernel_size = 0, initrd_size = 0; char boot_device; @@ -263,10 +269,27 @@ static void ibm_40p_init(MachineState *machine) cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); qemu_register_reset(ppc_prep_reset, cpu); + /* allocate and load firmware */ + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (!filename) { + error_report("Could not find bios image '%s'", bios_name); + exit(1); + } + memory_region_init_rom(bios, NULL, "bios", BIOS_SIZE, &error_fatal); + memory_region_add_subregion(get_system_memory(), BIOS_ADDR, bios); + bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); + if (bios_size < 0) { + bios_size = load_image_targphys(filename, BIOS_ADDR, BIOS_SIZE); + } + if (bios_size < 0 || bios_size > BIOS_SIZE) { + error_report("Could not load bios image '%s'", filename); + return; + } + g_free(filename); + /* PCI host */ dev = qdev_new("raven-pcihost"); - qdev_prop_set_string(dev, "bios-name", bios_name); - qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); pcihost = SYS_BUS_DEVICE(dev); object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); sysbus_realize_and_unref(pcihost, &error_fatal); From 17612f972f02fcafae2c70aa96c9d2e7a4c6d36d Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Wed, 14 May 2025 16:49:55 +0800 Subject: [PATCH 05/24] hw/core/resetcontainer: Consolidate OBJECT_DECLARE_SIMPLE_TYPE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QOM type of ResettableContainer is defined by OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES, which means it doesn't need the class! Therefore, use OBJECT_DECLARE_SIMPLE_TYPE to declare the type, then there's no need for class definition. Cc: Peter Maydell Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250514084957.2221975-8-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/resetcontainer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/core/resetcontainer.h b/include/hw/core/resetcontainer.h index 23db0c7a88..daeb18c1ea 100644 --- a/include/hw/core/resetcontainer.h +++ b/include/hw/core/resetcontainer.h @@ -20,7 +20,7 @@ #include "qom/object.h" #define TYPE_RESETTABLE_CONTAINER "resettable-container" -OBJECT_DECLARE_TYPE(ResettableContainer, ResettableContainerClass, RESETTABLE_CONTAINER) +OBJECT_DECLARE_SIMPLE_TYPE(ResettableContainer, RESETTABLE_CONTAINER) /** * resettable_container_add: Add a resettable object to the container From 8cab2354a2ff77c0977ac337a93ad6f645e5086a Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Wed, 14 May 2025 16:49:53 +0800 Subject: [PATCH 06/24] hw/hyperv/balloon: Consolidate OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QOM type of HvBalloon is declared by OBJECT_DECLARE_SIMPLE_TYPE, which means it doesn't need the class! Therefore, use OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES to implement the type, then there's no need for class definition. Cc: "Maciej S. Szmigiero" Signed-off-by: Zhao Liu Acked-by: Maciej S. Szmigiero Message-ID: <20250514084957.2221975-6-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/hyperv/hv-balloon.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/hyperv/hv-balloon.c b/hw/hyperv/hv-balloon.c index 94b0abbd68..6dbcb2d9a2 100644 --- a/hw/hyperv/hv-balloon.c +++ b/hw/hyperv/hv-balloon.c @@ -67,10 +67,6 @@ * these requests */ -struct HvBalloonClass { - VMBusDeviceClass parent_class; -} HvBalloonClass; - typedef enum State { /* not a real state */ S_NO_CHANGE = 0, @@ -162,8 +158,9 @@ typedef struct HvBalloon { MemoryRegion *mr; } HvBalloon; -OBJECT_DEFINE_TYPE_WITH_INTERFACES(HvBalloon, hv_balloon, HV_BALLOON, VMBUS_DEVICE, \ - { TYPE_MEMORY_DEVICE }, { }) +OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(HvBalloon, hv_balloon, \ + HV_BALLOON, VMBUS_DEVICE, \ + { TYPE_MEMORY_DEVICE }, { }) #define HV_BALLOON_SET_STATE(hvb, news) \ do { \ From ea585b1022f7c1ac6e465aa1fe869de4c20ca943 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 23 May 2025 17:02:11 +0200 Subject: [PATCH 07/24] hw/ppc/e500: Move clock and TB frequency to machine class MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Different machines have different frequencies so make this configurable in machine class instead of using a hard coded constant. Signed-off-by: BALATON Zoltan Acked-by: Bernhard Beschow Message-ID: <431166f96ff12ff3dbc670d40544974415f11305.1748012109.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/e500.c | 18 +++++++++--------- hw/ppc/e500.h | 4 ++++ hw/ppc/e500plat.c | 2 ++ hw/ppc/mpc8544ds.c | 2 ++ 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 809078a2c3..dedd96b057 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -79,8 +79,6 @@ #define MPC85XX_ESDHC_IRQ 72 #define RTC_REGS_OFFSET 0x68 -#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) - struct boot_info { uint32_t dt_base; @@ -120,7 +118,7 @@ static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, } static void dt_serial_create(void *fdt, unsigned long long offset, - const char *soc, const char *mpic, + const char *soc, uint32_t freq, const char *mpic, const char *alias, int idx, bool defcon) { char *ser; @@ -131,7 +129,7 @@ static void dt_serial_create(void *fdt, unsigned long long offset, qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); - qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ); + qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", freq); qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); @@ -382,8 +380,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms, int fdt_size; void *fdt; uint8_t hypercall[16]; - uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; - uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; + uint32_t clock_freq, tb_freq; int i; char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; char *soc; @@ -484,6 +481,9 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms, if (kvmppc_get_hasidle(env)) { qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); } + } else { + clock_freq = pmc->clock_freq; + tb_freq = pmc->tb_freq; } /* Create CPU nodes */ @@ -564,12 +564,12 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms, */ if (serial_hd(1)) { dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, - soc, mpic, "serial1", 1, false); + soc, pmc->clock_freq, mpic, "serial1", 1, false); } if (serial_hd(0)) { dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, - soc, mpic, "serial0", 0, true); + soc, pmc->clock_freq, mpic, "serial0", 0, true); } /* i2c */ @@ -968,7 +968,7 @@ void ppce500_init(MachineState *machine) env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; - ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); + ppc_booke_timers_init(cpu, pmc->tb_freq, PPC_TIMER_E500); /* Register reset handler */ if (!i) { diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 01db102625..00f490519c 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -5,6 +5,8 @@ #include "hw/platform-bus.h" #include "qom/object.h" +#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) + struct PPCE500MachineState { /*< private >*/ MachineState parent_obj; @@ -37,6 +39,8 @@ struct PPCE500MachineClass { hwaddr pci_mmio_base; hwaddr pci_mmio_bus_base; hwaddr spin_base; + uint32_t clock_freq; + uint32_t tb_freq; }; void ppce500_init(MachineState *machine); diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 775b9d8da0..4f1d659e72 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -93,6 +93,8 @@ static void e500plat_machine_class_init(ObjectClass *oc, const void *data) pmc->pci_mmio_base = 0xC00000000ULL; pmc->pci_mmio_bus_base = 0xE0000000ULL; pmc->spin_base = 0xFEF000000ULL; + pmc->clock_freq = PLATFORM_CLK_FREQ_HZ; + pmc->tb_freq = PLATFORM_CLK_FREQ_HZ; mc->desc = "generic paravirt e500 platform"; mc->init = e500plat_init; diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index 97fb0f35ba..582698559d 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -55,6 +55,8 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, const void *data) pmc->pci_mmio_bus_base = 0xC0000000ULL; pmc->pci_pio_base = 0xE1000000ULL; pmc->spin_base = 0xEF000000ULL; + pmc->clock_freq = PLATFORM_CLK_FREQ_HZ; + pmc->tb_freq = PLATFORM_CLK_FREQ_HZ; mc->desc = "mpc8544ds"; mc->init = mpc8544ds_init; From 3c32fa9fb2300bbe435fc417dbb521981e230639 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 23 May 2025 17:02:12 +0200 Subject: [PATCH 08/24] hw/net/fsl_etsec: Set default MAC address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use default MAC address if none is specified by property as done by most other network interface models. Signed-off-by: BALATON Zoltan Reviewed-by: Bernhard Beschow Acked-by: Bernhard Beschow Message-ID: <8bd7ca691bd502b5fd761615d9af805e783fba36.1748012109.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/net/fsl_etsec/etsec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index d14cb2a101..846f6cbc5d 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -389,6 +389,7 @@ static void etsec_realize(DeviceState *dev, Error **errp) { eTSEC *etsec = ETSEC_COMMON(dev); + qemu_macaddr_default_if_unset(&etsec->conf.macaddr); etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf, object_get_typename(OBJECT(dev)), dev->id, &dev->mem_reentrancy_guard, etsec); From a35391ba87651daeafa02231e842ae28c349cac0 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Fri, 23 May 2025 17:02:13 +0200 Subject: [PATCH 09/24] hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resources MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rather than accessing the attributes of TYPE_CCSR directly, use the SysBusDevice API which exists exactly for that purpose. Furthermore, registering the memory region with the SysBusDevice API makes it show up in QMP's `info qom-tree` command. Signed-off-by: Bernhard Beschow Reviewed-by: BALATON Zoltan [balaton: rebased] Signed-off-by: BALATON Zoltan Acked-by: Bernhard Beschow Message-ID: <619a58d1f83d2aad5b4feec930d46c64abff0977.1748012109.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/ppce500.c | 8 ++++---- hw/ppc/e500.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index e97a515d5f..52269b05bb 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -16,7 +16,6 @@ #include "qemu/osdep.h" #include "hw/irq.h" -#include "hw/ppc/e500-ccsr.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "hw/pci/pci_device.h" @@ -418,11 +417,12 @@ static const VMStateDescription vmstate_ppce500_pci = { static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) { PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); - PPCE500CCSRState *ccsr = CCSR( + SysBusDevice *ccsr = SYS_BUS_DEVICE( object_resolve_path_component(qdev_get_machine(), "e500-ccsr")); + MemoryRegion *ccsr_space = sysbus_mmio_get_region(ccsr, 0); - memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, - 0, int128_get64(ccsr->ccsr_space.size)); + memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", + ccsr_space, 0, int128_get64(ccsr_space->size)); pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); } diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index dedd96b057..6899802bed 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -931,7 +931,6 @@ void ppce500_init(MachineState *machine) CPUPPCState *firstenv = NULL; MemoryRegion *ccsr_addr_space; SysBusDevice *s; - PPCE500CCSRState *ccsr; I2CBus *i2c; irqs = g_new0(IrqLines, smp_cpus); @@ -993,10 +992,10 @@ void ppce500_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0, machine->ram); dev = qdev_new("e500-ccsr"); + s = SYS_BUS_DEVICE(dev); object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - ccsr = CCSR(dev); - ccsr_addr_space = &ccsr->ccsr_space; + sysbus_realize_and_unref(s, &error_fatal); + ccsr_addr_space = sysbus_mmio_get_region(s, 0); memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, ccsr_addr_space); @@ -1284,6 +1283,7 @@ static void e500_ccsr_initfn(Object *obj) PPCE500CCSRState *ccsr = CCSR(obj); memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", MPC8544_CCSRBAR_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space); } static const TypeInfo e500_ccsr_info = { From bebcf2cff4091281ddf67240d5651ed7938ea83a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Date: Fri, 30 May 2025 16:21:18 +0100 Subject: [PATCH 10/24] pc-bios: ensure installed ROMs don't have execute permissions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have been inconsistent about whether ROMS stored in git have execute permission set, and by default meson will preserve source file permissions when installing files. This has caused periodic problems in RPM packaging as executable binary files get analysed by various tools/linters, which can trip up on the ROMs. Tell meson explicitly that all the ROMs should be without execute permission when installed. Signed-off-by: Daniel P. Berrangé Reviewed-by: Helge Deller Tested-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250530152118.65030-1-berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- pc-bios/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pc-bios/meson.build b/pc-bios/meson.build index 79bb2e1800..3c41620044 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -88,7 +88,7 @@ blobs = [ ] if get_option('install_blobs') - install_data(blobs, install_dir: qemu_datadir) + install_data(blobs, install_dir: qemu_datadir, install_mode: 'rw-r--r--') endif subdir('descriptors') From f37efe50d4a234f30cf6dde0bdcf4e75a798a123 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Sat, 31 May 2025 16:00:25 +0900 Subject: [PATCH 11/24] MAINTAINERS: Update Akihiko Odaki's affiliation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit My contract with Daynix Computing Ltd. will expire by the end of May, 2025. As I may contribute to QEMU for my research, use my email address at the lab. As I'm the only maintainer of igb and no longer financially supported to maintain it, change its status to Odd Fixes until someone steps up. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250531-rsg-v1-1-e0bae1e1d90e@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Philippe Mathieu-Daudé --- .mailmap | 3 ++- MAINTAINERS | 16 ++++++++-------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/.mailmap b/.mailmap index 33fe75400f..e7271852dc 100644 --- a/.mailmap +++ b/.mailmap @@ -67,7 +67,8 @@ Andrey Drobyshev Andrey Drobyshev via BALATON Zoltan via # Next, replace old addresses by a more recent one. -Akihiko Odaki +Akihiko Odaki +Akihiko Odaki Aleksandar Markovic Aleksandar Markovic Aleksandar Markovic diff --git a/MAINTAINERS b/MAINTAINERS index aa6763077e..76399ad1e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2519,7 +2519,7 @@ F: tests/qtest/fuzz-megasas-test.c Network packet abstractions M: Dmitry Fleytman -R: Akihiko Odaki +R: Akihiko Odaki S: Maintained F: include/net/eth.h F: net/eth.c @@ -2549,13 +2549,13 @@ F: docs/specs/rocker.rst e1000x M: Dmitry Fleytman -R: Akihiko Odaki +R: Akihiko Odaki S: Maintained F: hw/net/e1000x* e1000e M: Dmitry Fleytman -R: Akihiko Odaki +R: Akihiko Odaki S: Maintained F: hw/net/e1000e* F: tests/qtest/fuzz-e1000e-test.c @@ -2563,9 +2563,9 @@ F: tests/qtest/e1000e-test.c F: tests/qtest/libqos/e1000e.* igb -M: Akihiko Odaki +M: Akihiko Odaki R: Sriram Yagnaraman -S: Maintained +S: Odd Fixes F: docs/system/devices/igb.rst F: hw/net/igb* F: tests/functional/test_netdev_ethtool.py @@ -2910,7 +2910,7 @@ Core Audio framework backend M: Gerd Hoffmann M: Philippe Mathieu-Daudé R: Christian Schoenebeck -R: Akihiko Odaki +R: Akihiko Odaki S: Odd Fixes F: audio/coreaudio.m @@ -3211,7 +3211,7 @@ F: tests/functional/test_vnc.py Cocoa graphics M: Peter Maydell M: Philippe Mathieu-Daudé -R: Akihiko Odaki +R: Akihiko Odaki S: Odd Fixes F: ui/cocoa.m @@ -3738,7 +3738,7 @@ F: util/iova-tree.c elf2dmp M: Viktor Prutyanov -R: Akihiko Odaki +R: Akihiko Odaki S: Maintained F: contrib/elf2dmp/ From ff1bc6f4c5be7315dcd3970f7bff6b4f986db877 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 3 Jun 2025 20:40:05 +0200 Subject: [PATCH 12/24] tests/functional: Add a test for the Arduino UNO machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check whether we can run a kernel that prints something to the serial console. Signed-off-by: Thomas Huth Reviewed-by: Mark Cave-Ayland Message-ID: <20250603184007.24521-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 3 ++- tests/functional/meson.build | 1 + tests/functional/test_avr_uno.py | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) create mode 100755 tests/functional/test_avr_uno.py diff --git a/MAINTAINERS b/MAINTAINERS index 76399ad1e0..a6f210dba5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -219,7 +219,7 @@ S: Maintained F: docs/system/target-avr.rst F: gdb-xml/avr-cpu.xml F: target/avr/ -F: tests/functional/test_avr_mega2560.py +F: tests/functional/test_avr_*.py Hexagon TCG CPUs M: Brian Cain @@ -1236,6 +1236,7 @@ Arduino M: Philippe Mathieu-Daudé S: Maintained F: hw/avr/arduino.c +F: tests/functional/test_avr_uno.py HP-PARISC Machines ------------------ diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 557d59ddf4..e406451cd3 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -150,6 +150,7 @@ tests_arm_linuxuser_thorough = [ tests_avr_system_thorough = [ 'avr_mega2560', + 'avr_uno', ] tests_hppa_system_quick = [ diff --git a/tests/functional/test_avr_uno.py b/tests/functional/test_avr_uno.py new file mode 100755 index 0000000000..adb3b73da4 --- /dev/null +++ b/tests/functional/test_avr_uno.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# +# QEMU AVR Arduino UNO functional test +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset, wait_for_console_pattern + + +class UnoMachine(QemuSystemTest): + + ASSET_UNO = Asset( + ('https://github.com/RahulRNandan/LED_Blink_AVR/raw/' + 'c6d602cbb974a193/build/main.elf'), + '3009a4e2cf5c5b65142f538abdf66d4dc6bc6beab7e552fff9ae314583761b72') + + def test_uno(self): + """ + The binary constantly prints out 'LED Blink' + """ + self.set_machine('arduino-uno') + rom_path = self.ASSET_UNO.fetch() + + self.vm.add_args('-bios', rom_path) + self.vm.set_console() + self.vm.launch() + + wait_for_console_pattern(self, 'LED Blink') + + +if __name__ == '__main__': + QemuSystemTest.main() From 6cfe590c6b7876ba2471a4357274b33072d62214 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 5 Jun 2025 08:20:37 +0200 Subject: [PATCH 13/24] accel/hvf: Fix TYPE_HVF_ACCEL instance size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes: c97d6d2cdf9 ("i386: hvf: add code base from Google repo") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250606164418.98655-7-philmd@linaro.org> --- accel/hvf/hvf-accel-ops.c | 1 + include/system/hvf_int.h | 1 + 2 files changed, 2 insertions(+) diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index b8b6116bc8..d60446b85b 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -366,6 +366,7 @@ static void hvf_accel_class_init(ObjectClass *oc, const void *data) static const TypeInfo hvf_accel_type = { .name = TYPE_HVF_ACCEL, .parent = TYPE_ACCEL, + .instance_size = sizeof(HVFState), .class_init = hvf_accel_class_init, }; diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h index 8c8b84012d..d774e58df9 100644 --- a/include/system/hvf_int.h +++ b/include/system/hvf_int.h @@ -44,6 +44,7 @@ typedef struct hvf_vcpu_caps { struct HVFState { AccelState parent; + hvf_slot slots[32]; int num_slots; From 59a4757bb4d01c9dfb50e872a9d04ad1f1c38049 Mon Sep 17 00:00:00 2001 From: Zhao Liu Date: Thu, 5 Jun 2025 21:27:22 +0800 Subject: [PATCH 14/24] hw/core/cpu: Move CacheType to general cpu.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I386 has already defined cache types in target/i386/cpu.h. Move CacheType to hw/core/cpu.h, so that ARM and other architectures could use it. Cc: Alireza Sanaee Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250605132722.3597593-1-zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 6 ++++++ target/i386/cpu.h | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1e87f7d393..33296a1c08 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1126,4 +1126,10 @@ extern const VMStateDescription vmstate_cpu_common; #define UNASSIGNED_CPU_INDEX -1 #define UNASSIGNED_CLUSTER_INDEX -1 +enum CacheType { + DATA_CACHE, + INSTRUCTION_CACHE, + UNIFIED_CACHE +}; + #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 545851cbde..5910dcf74d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1773,12 +1773,6 @@ typedef enum TPRAccess { /* Cache information data structures: */ -enum CacheType { - DATA_CACHE, - INSTRUCTION_CACHE, - UNIFIED_CACHE -}; - typedef struct CPUCacheInfo { enum CacheType type; uint8_t level; From c7785e243195799749242b5fc741b8fbf1053f82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 5 Jun 2025 19:56:52 +0200 Subject: [PATCH 15/24] hw/gpio/pca9552: Avoid using g_newa() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have pin_count <= PCA955X_PIN_COUNT_MAX. Having PCA955X_PIN_COUNT_MAX = 16, it is safe to explicitly allocate the char buffer on the stack, without g_newa(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Glenn Miles Reviewed-by: Stefan Hajnoczi Message-Id: <20250605193540.59874-2-philmd@linaro.org> --- hw/gpio/pca9552.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/gpio/pca9552.c b/hw/gpio/pca9552.c index d65c0a2e90..1e10238b2e 100644 --- a/hw/gpio/pca9552.c +++ b/hw/gpio/pca9552.c @@ -76,7 +76,7 @@ static void pca955x_display_pins_status(PCA955xState *s, return; } if (trace_event_get_state_backends(TRACE_PCA955X_GPIO_STATUS)) { - char *buf = g_newa(char, k->pin_count + 1); + char buf[PCA955X_PIN_COUNT_MAX + 1]; for (i = 0; i < k->pin_count; i++) { if (extract32(pins_status, i, 1)) { From 0ff9cd9a6af54ccaa293e252aa356fb150788099 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 5 Jun 2025 19:54:58 +0200 Subject: [PATCH 16/24] backends/tpm: Avoid using g_alloca() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit tpm_emulator_ctrlcmd() is not in hot path. Use the heap instead of the stack, removing the g_alloca() call. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Thomas Huth Reviewed-by: Stefan Berger Reviewed-by: Stefan Hajnoczi Message-Id: <20250605193540.59874-3-philmd@linaro.org> --- backends/tpm/tpm_emulator.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/tpm/tpm_emulator.c b/backends/tpm/tpm_emulator.c index 43d350e895..4a234ab2c0 100644 --- a/backends/tpm/tpm_emulator.c +++ b/backends/tpm/tpm_emulator.c @@ -129,11 +129,11 @@ static int tpm_emulator_ctrlcmd(TPMEmulator *tpm, unsigned long cmd, void *msg, CharBackend *dev = &tpm->ctrl_chr; uint32_t cmd_no = cpu_to_be32(cmd); ssize_t n = sizeof(uint32_t) + msg_len_in; - uint8_t *buf = NULL; ptm_res res; WITH_QEMU_LOCK_GUARD(&tpm->mutex) { - buf = g_alloca(n); + g_autofree uint8_t *buf = g_malloc(n); + memcpy(buf, &cmd_no, sizeof(cmd_no)); memcpy(buf + sizeof(cmd_no), msg, msg_len_in); From 2f014eabc1acc64c403557f5a51fdb1ba43bbdd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 5 Jun 2025 21:20:23 +0200 Subject: [PATCH 17/24] tests/unit/test-char: Avoid using g_alloca() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not use g_alloca(), simply allocate the CharBackend structure on the stack. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Stefan Hajnoczi Message-Id: <20250605193540.59874-4-philmd@linaro.org> --- tests/unit/test-char.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/unit/test-char.c b/tests/unit/test-char.c index 60a843b79d..f30a39f61f 100644 --- a/tests/unit/test-char.c +++ b/tests/unit/test-char.c @@ -993,7 +993,7 @@ static void char_udp_test_internal(Chardev *reuse_chr, int sock) struct sockaddr_in other; SocketIdleData d = { 0, }; Chardev *chr; - CharBackend *be; + CharBackend stack_be, *be = &stack_be; socklen_t alen = sizeof(other); int ret; char buf[10]; @@ -1009,7 +1009,6 @@ static void char_udp_test_internal(Chardev *reuse_chr, int sock) chr = qemu_chr_new("client", tmp, NULL); g_assert_nonnull(chr); - be = g_alloca(sizeof(CharBackend)); qemu_chr_fe_init(be, chr, &error_abort); } From 61c4c2558df16262db34397cf50a16ad7b725731 Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Fri, 6 Jun 2025 17:24:02 +0800 Subject: [PATCH 18/24] hw/virtio/virtio-mem: Fix definition of VirtIOMEMClass MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Parent of VirtIOMEMClass is VirtioDeviceClass rather than VirtIODevice. This isn't catastrophic only because sizeof(VirtIODevice) > sizeof(VirtioDeviceClass). Fixes: 910b25766b33 ("virtio-mem: Paravirtualized memory hot(un)plug") Signed-off-by: Zhenzhong Duan Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250606092406.229833-2-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/virtio/virtio-mem.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/virtio/virtio-mem.h b/include/hw/virtio/virtio-mem.h index bc4f787772..e0ab31b45a 100644 --- a/include/hw/virtio/virtio-mem.h +++ b/include/hw/virtio/virtio-mem.h @@ -134,7 +134,7 @@ struct VirtioMemSystemReset { struct VirtIOMEMClass { /* private */ - VirtIODevice parent; + VirtioDeviceClass parent_class; /* public */ void (*fill_device_info)(const VirtIOMEM *vmen, VirtioMEMDeviceInfo *vi); From 747a7ee3741fa9876583cbbbc8dd8b8b351a199c Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Fri, 6 Jun 2025 17:24:03 +0800 Subject: [PATCH 19/24] hw/virtio/virtio-pmem: Fix definition of VirtIOPMEMClass MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VirtIOPMEMClass's parent is VirtioDeviceClass rather than VirtIODevice. This isn't catastrophic only because sizeof(VirtIODevice) > sizeof(VirtioDeviceClass). Fixes: 5f503cd9f388 ("virtio-pmem: add virtio device") Closes: https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg00586.html Reported-by: David Hildenbrand Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Zhenzhong Duan Message-ID: <20250606092406.229833-3-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/virtio/virtio-pmem.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/virtio/virtio-pmem.h b/include/hw/virtio/virtio-pmem.h index fc4fd1f7fe..9cce600d0b 100644 --- a/include/hw/virtio/virtio-pmem.h +++ b/include/hw/virtio/virtio-pmem.h @@ -36,7 +36,7 @@ struct VirtIOPMEM { struct VirtIOPMEMClass { /* private */ - VirtIODevice parent; + VirtioDeviceClass parent_class; /* public */ void (*fill_device_info)(const VirtIOPMEM *pmem, VirtioPMEMDeviceInfo *vi); From 2f8f01ae3d6b7acae187d700d7358d9bb248a696 Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Fri, 6 Jun 2025 17:24:04 +0800 Subject: [PATCH 20/24] hw/gpio/aspeed: Fix definition of AspeedGPIOClass MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AspeedGPIOClass's parent is SysBusDeviceClass rather than SysBusDevice. This isn't catastrophic only because sizeof(SysBusDevice) > sizeof(SysBusDeviceClass). Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Closes: https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg00586.html Suggested-by: David Hildenbrand Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Zhenzhong Duan Message-ID: <20250606092406.229833-4-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/gpio/aspeed_gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index e1e6c54333..e6b2fe71b5 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -70,7 +70,7 @@ typedef struct AspeedGPIOReg { } AspeedGPIOReg; struct AspeedGPIOClass { - SysBusDevice parent_obj; + SysBusDeviceClass parent_class; const GPIOSetProperties *props; uint32_t nr_gpio_pins; uint32_t nr_gpio_sets; From 860bb8b925418f3ea55305da2a7387d8318ac00c Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Fri, 6 Jun 2025 17:24:06 +0800 Subject: [PATCH 21/24] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed parent class, class_init on them may corrupt their parent class fields. It's lucky that parent_realize and parent_phases are not initialized or used until now, so just remove the definitions. They can be added back when really necessary. Signed-off-by: Zhenzhong Duan Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20250606092406.229833-6-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/riscv-iommu-pci.c | 6 ------ hw/riscv/riscv-iommu-sys.c | 6 ------ include/hw/riscv/iommu.h | 6 ++---- 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index 1f44eef74e..cdb4a7a8f0 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -68,12 +68,6 @@ typedef struct RISCVIOMMUStatePci { RISCVIOMMUState iommu; /* common IOMMU state */ } RISCVIOMMUStatePci; -struct RISCVIOMMUPciClass { - /*< public >*/ - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - /* interrupt delivery callback */ static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) { diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index 74e76b94a5..e34d00aef6 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -53,12 +53,6 @@ struct RISCVIOMMUStateSys { uint8_t *msix_pba; }; -struct RISCVIOMMUSysClass { - /*< public >*/ - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, unsigned size) { diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h index b03339d75c..8a8acfc3f0 100644 --- a/include/hw/riscv/iommu.h +++ b/include/hw/riscv/iommu.h @@ -30,14 +30,12 @@ typedef struct RISCVIOMMUState RISCVIOMMUState; typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; #define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci" -OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI) +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; -typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass; #define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" -OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS) +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; -typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass; #define FDT_IRQ_TYPE_EDGE_LOW 1 From 3938180c9c58b61b38c7fc304eb48b903c7dfd87 Mon Sep 17 00:00:00 2001 From: Philippe Michaud-Boudreault Date: Sat, 7 Jun 2025 09:33:01 -0400 Subject: [PATCH 22/24] hw/misc/stm32_rcc: Fix stm32_rcc_write() arguments order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The tracing function for the write case incorrectly has parameters switched around. So order them in the correct way. Signed-off-by: Philippe Michaud-Boudreault Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/stm32_rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/stm32_rcc.c b/hw/misc/stm32_rcc.c index 94e8dae441..5815b3efa5 100644 --- a/hw/misc/stm32_rcc.c +++ b/hw/misc/stm32_rcc.c @@ -60,7 +60,7 @@ static void stm32_rcc_write(void *opaque, hwaddr addr, uint32_t value = val64; uint32_t prev_value, new_value, irq_offset; - trace_stm32_rcc_write(value, addr); + trace_stm32_rcc_write(addr, value); if (addr > STM32_RCC_DCKCFGR2) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n", From 32e02fd3886c01a5c1c888ecd1e5035f851717a1 Mon Sep 17 00:00:00 2001 From: Soumyajyotii Ssarkar Date: Sat, 7 Jun 2025 20:57:12 +0530 Subject: [PATCH 23/24] hw/net/i82596: Update datasheet URL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the asset link to one which is working from the PARISC website. Signed-off-by: Soumyajyotii Ssarkar Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250607152711.108914-2-soumyajyotisarkar23@gmail.com> [PMD: Split patch in 2] Signed-off-by: Philippe Mathieu-Daudé --- hw/net/i82596.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/i82596.c b/hw/net/i82596.c index 64ed3c8390..fc33a00d49 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -5,7 +5,7 @@ * This work is licensed under the GNU GPL license version 2 or later. * * This software was written to be compatible with the specification: - * https://www.intel.com/assets/pdf/general/82596ca.pdf + * https://parisc.docs.kernel.org/en/latest/_downloads/96672be0650d9fc046bbcea40b92482f/82596CA.pdf */ #include "qemu/osdep.h" From fb8449def4a22d8e65e9773c923174ae2c1db893 Mon Sep 17 00:00:00 2001 From: Soumyajyotii Ssarkar Date: Sat, 7 Jun 2025 20:57:12 +0530 Subject: [PATCH 24/24] hw/net/i82596: Factor configure function out MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Abstract the configure function. Signed-off-by: Soumyajyotii Ssarkar Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250607152711.108914-2-soumyajyotisarkar23@gmail.com> [PMD: Split patch in 2] Signed-off-by: Philippe Mathieu-Daudé --- hw/net/i82596.c | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/hw/net/i82596.c b/hw/net/i82596.c index fc33a00d49..c1ff3e6c56 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -177,6 +177,26 @@ static void set_individual_address(I82596State *s, uint32_t addr) trace_i82596_new_mac(nc->info_str); } +static void i82596_configure(I82596State *s, uint32_t addr) +{ + uint8_t byte_cnt; + byte_cnt = get_byte(addr + 8) & 0x0f; + + byte_cnt = MAX(byte_cnt, 4); + byte_cnt = MIN(byte_cnt, sizeof(s->config)); + /* copy byte_cnt max. */ + address_space_read(&address_space_memory, addr + 8, + MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt); + /* config byte according to page 35ff */ + s->config[2] &= 0x82; /* mask valid bits */ + s->config[2] |= 0x40; + s->config[7] &= 0xf7; /* clear zero bit */ + assert(I596_NOCRC_INS == 0); /* do CRC insertion */ + s->config[10] = MAX(s->config[10], 5); /* min frame length */ + s->config[12] &= 0x40; /* only full duplex field valid */ + s->config[13] |= 0x3f; /* set ones in byte 13 */ +} + static void set_multicast_list(I82596State *s, uint32_t addr) { uint16_t mc_count, i; @@ -234,7 +254,6 @@ static void command_loop(I82596State *s) { uint16_t cmd; uint16_t status; - uint8_t byte_cnt; DBG(printf("STARTING COMMAND LOOP cmd_p=%08x\n", s->cmd_p)); @@ -254,20 +273,7 @@ static void command_loop(I82596State *s) set_individual_address(s, s->cmd_p); break; case CmdConfigure: - byte_cnt = get_byte(s->cmd_p + 8) & 0x0f; - byte_cnt = MAX(byte_cnt, 4); - byte_cnt = MIN(byte_cnt, sizeof(s->config)); - /* copy byte_cnt max. */ - address_space_read(&address_space_memory, s->cmd_p + 8, - MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt); - /* config byte according to page 35ff */ - s->config[2] &= 0x82; /* mask valid bits */ - s->config[2] |= 0x40; - s->config[7] &= 0xf7; /* clear zero bit */ - assert(I596_NOCRC_INS == 0); /* do CRC insertion */ - s->config[10] = MAX(s->config[10], 5); /* min frame length */ - s->config[12] &= 0x40; /* only full duplex field valid */ - s->config[13] |= 0x3f; /* set ones in byte 13 */ + i82596_configure(s, s->cmd_p); break; case CmdTDR: /* get signal LINK */