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hw/acpi: Generic Port Affinity Structure support

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These are very similar to the recently added Generic Initiators
but instead of representing an initiator of memory traffic they
represent an edge point beyond which may lie either targets or
initiators.  Here we add these ports such that they may
be targets of hmat_lb records to describe the latency and
bandwidth from host side initiators to the port.  A discoverable
mechanism such as UEFI CDAT read from CXL devices and switches
is used to discover the remainder of the path, and the OS can build
up full latency and bandwidth numbers as need for work and data
placement decisions.

Acked-by: Markus Armbruster <armbru@redhat.com>
Tested-by: "Huang, Ying" <ying.huang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240916174122.1843197-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron
2024-11-04 16:03:24 -05:00
committed by Michael S. Tsirkin
parent 43eb5e1f73
commit a82fe82916
9 changed files with 202 additions and 5 deletions
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qapi/qom.json
+41
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@@ -844,6 +844,45 @@
'data': { 'pci-dev': 'str',
'node': 'uint32' } }
##
# @AcpiGenericPortProperties:
#
# Properties for acpi-generic-port objects.
#
# @pci-bus: QOM path of the PCI bus of the hostbridge associated with
# this SRAT Generic Port Affinity Structure. This is the same as
# the bus parameter for the root ports attached to this host
# bridge. The resulting SRAT Generic Port Affinity Structure will
# refer to the ACPI object in DSDT that represents the host bridge
# (e.g. ACPI0016 for CXL host bridges). See ACPI 6.5 Section
# 5.2.16.7 for more information.
#
# @node: Similar to a NUMA node ID, but instead of providing a
# reference point used for defining NUMA distances and access
# characteristics to memory or from an initiator (e.g. CPU), this
# node defines the boundary point between non-discoverable system
# buses which must be described by firmware, and a discoverable
# bus. NUMA distances and access characteristics are defined to
# and from that point. For system software to establish full
# initiator to target characteristics this information must be
# combined with information retrieved from the discoverable part
# of the path. An example would use CDAT (see UEFI.org)
# information read from devices and switches in conjunction with
# link characteristics read from PCIe Configuration space.
# To get the full path latency from CPU to CXL attached DRAM
# CXL device: Add the latency from CPU to Generic Port (from
# HMAT indexed via the the node ID in this SRAT structure) to
# that for CXL bus links, the latency across intermediate switches
# and from the EP port to the actual memory. Bandwidth is more
# complex as there may be interleaving across multiple devices
# and shared links in the path.
#
# Since: 9.1
##
{ 'struct': 'AcpiGenericPortProperties',
'data': { 'pci-bus': 'str',
'node': 'uint32' } }
##
# @RngProperties:
#
@@ -1043,6 +1082,7 @@
{ 'enum': 'ObjectType',
'data': [
'acpi-generic-initiator',
'acpi-generic-port',
'authz-list',
'authz-listfile',
'authz-pam',
@@ -1118,6 +1158,7 @@
'discriminator': 'qom-type',
'data': {
'acpi-generic-initiator': 'AcpiGenericInitiatorProperties',
'acpi-generic-port': 'AcpiGenericPortProperties',
'authz-list': 'AuthZListProperties',
'authz-listfile': 'AuthZListFileProperties',
'authz-pam': 'AuthZPAMProperties',