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target/arm: Implement FEAT_SCTLR2 and enable with -cpu max
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx ones. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250727074202.83141-4-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-4-gustavo.romero@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell
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@@ -121,6 +121,7 @@ the following architecture extensions:
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- FEAT_RPRES (Increased precision of FRECPE and FRSQRTE)
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- FEAT_S2FWB (Stage 2 forced Write-Back)
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- FEAT_SB (Speculation Barrier)
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- FEAT_SCTLR2 (Extension to SCTLR_ELx)
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- FEAT_SEL2 (Secure EL2)
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- FEAT_SHA1 (SHA1 instructions)
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- FEAT_SHA256 (SHA256 instructions)
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