mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into staging
Removal of deprecated code - Remove the Nios II target and hardware - Remove pvrdma device and rdmacm-mux helper - Remove GlusterFS RDMA protocol handling - Update Sriram Yagnaraman mail address # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYpE0YACgkQ4+MsLN6t # wN5PIA//egomANjRHAUAf9tdjljgT/JR49ejM7iInyxspR/xaiq0TlP2kP6aDNps # y1HAWBwfj5lGxeMgQ1mSKJGka3v2AIPWb7RbNT+9AaiWHv+sx5OrEytozUsFHLo8 # gSgRQocq0NY2a9dPbtkDqfbmq/rkCC7wgZzwroHsyOdiqYsWDKPJFleBDMjGmEaf # colhiDmhUPgvE3NNpwfEVNh/2SzxUxY8k5FHal6qij5z56ZqBglgnziDZEvGVCZ1 # uF4Hca/kh7TV2MVsdStPbGWZYDhJ/Np/2FnRoThD1Hc4qq8d/SH997m2F94tSOud # YeH54Vp5lmCeYgba5y8VP0ZPx/b9XnTtLvKggNdoqB+T2LBWPRt8kehqoaxvammF # ALzbY/t2vUxL6nIVbosOaTyqVOXvynk3/Js5S0jbnlu+vP2WvvFEzfYKIs2DIA8w # z56o/rG4KfyxF0aDB+CvLNwtJS8THqeivPqmYoKTdN9FPpN2RyBNLITrKo389ygF # 3oWy3+xsKGIPdNFY0a4l25xntqWNhND89ejzyL9M6G1cQ9RdEmTIUGTrinPQQmfP # oHIJMBeTdj7EqPL4LB3BR/htw9U5PobeMNYKFsRkS39PjGDqba5wbIdk3w5/Rcxa # s/PKdspDKWPwZ5jhcLD0qxAGJFnqM2UFjPo+U8qyI3RXKXFAn0E= # =c8Aj # -----END PGP SIGNATURE----- # gpg: Signature made Wed 24 Apr 2024 07:12:22 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'housekeeping-20240424' of https://github.com/philmd/qemu: block/gluster: Remove deprecated RDMA protocol handling hw/rdma: Remove deprecated pvrdma device and rdmacm-mux helper hw/timer: Remove the ALTERA_TIMER model target/nios2: Remove the deprecated Nios II target MAINTAINERS: Update Sriram Yagnaraman mail address Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
@@ -241,10 +241,6 @@ enum bfd_architecture
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bfd_arch_ia64, /* HP/Intel ia64 */
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#define bfd_mach_ia64_elf64 64
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#define bfd_mach_ia64_elf32 32
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bfd_arch_nios2, /* Nios II */
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#define bfd_mach_nios2 0
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#define bfd_mach_nios2r1 1
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#define bfd_mach_nios2r2 2
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bfd_arch_rx, /* Renesas RX */
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#define bfd_mach_rx 0x75
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#define bfd_mach_rx_v2 0x76
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@@ -456,7 +452,6 @@ int print_insn_crisv32 (bfd_vma, disassemble_info*);
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int print_insn_crisv10 (bfd_vma, disassemble_info*);
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int print_insn_microblaze (bfd_vma, disassemble_info*);
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int print_insn_ia64 (bfd_vma, disassemble_info*);
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int print_insn_nios2(bfd_vma, disassemble_info*);
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int print_insn_xtensa (bfd_vma, disassemble_info*);
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int print_insn_riscv32 (bfd_vma, disassemble_info*);
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int print_insn_riscv64 (bfd_vma, disassemble_info*);
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@@ -22,7 +22,6 @@
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#pragma GCC poison TARGET_ABI_MIPSO32
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#pragma GCC poison TARGET_MIPS64
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#pragma GCC poison TARGET_ABI_MIPSN64
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#pragma GCC poison TARGET_NIOS2
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#pragma GCC poison TARGET_OPENRISC
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#pragma GCC poison TARGET_PPC
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#pragma GCC poison TARGET_PPC64
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@@ -73,7 +72,6 @@
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#pragma GCC poison CONFIG_M68K_DIS
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#pragma GCC poison CONFIG_MICROBLAZE_DIS
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#pragma GCC poison CONFIG_MIPS_DIS
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#pragma GCC poison CONFIG_NIOS2_DIS
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#pragma GCC poison CONFIG_PPC_DIS
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#pragma GCC poison CONFIG_RISCV_DIS
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#pragma GCC poison CONFIG_S390_DIS
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@@ -25,8 +25,7 @@
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#if (defined(TARGET_I386) && !defined(TARGET_X86_64)) \
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|| defined(TARGET_SH4) \
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|| defined(TARGET_OPENRISC) \
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|| defined(TARGET_MICROBLAZE) \
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|| defined(TARGET_NIOS2)
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|| defined(TARGET_MICROBLAZE)
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#define ABI_LLONG_ALIGNMENT 4
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#endif
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@@ -1,66 +0,0 @@
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/*
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* Vectored Interrupt Controller for nios2 processor
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*
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* Copyright (c) 2022 Neuroblade
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*
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* Interface:
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* QOM property "cpu": link to the Nios2 CPU (must be set)
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* Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
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* IRQ should be connected to nios2 IRQ0.
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*
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* Reference: "Embedded Peripherals IP User Guide
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* for Intel® Quartus® Prime Design Suite: 21.4"
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* Chapter 38 "Vectored Interrupt Controller Core"
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* See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_INTC_NIOS2_VIC_H
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#define HW_INTC_NIOS2_VIC_H
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#include "hw/sysbus.h"
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#define TYPE_NIOS2_VIC "nios2-vic"
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OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC)
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#define NIOS2_VIC_MAX_IRQ 32
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struct Nios2VIC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq output_int;
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/* properties */
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CPUState *cpu;
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MemoryRegion csr;
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uint32_t int_config[NIOS2_VIC_MAX_IRQ];
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uint32_t vic_config;
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uint32_t int_raw_status;
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uint32_t int_enable;
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uint32_t sw_int;
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uint32_t vic_status;
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uint32_t vec_tbl_base;
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uint32_t vec_tbl_addr;
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};
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#endif /* HW_INTC_NIOS2_VIC_H */
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@@ -1,37 +0,0 @@
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/*
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* RDMA device interface
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*
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* Copyright (C) 2019 Oracle
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* Copyright (C) 2019 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef RDMA_H
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#define RDMA_H
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#include "qom/object.h"
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#define INTERFACE_RDMA_PROVIDER "rdma"
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typedef struct RdmaProviderClass RdmaProviderClass;
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DECLARE_CLASS_CHECKERS(RdmaProviderClass, RDMA_PROVIDER,
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INTERFACE_RDMA_PROVIDER)
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#define RDMA_PROVIDER(obj) \
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INTERFACE_CHECK(RdmaProvider, (obj), \
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INTERFACE_RDMA_PROVIDER)
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typedef struct RdmaProvider RdmaProvider;
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struct RdmaProviderClass {
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InterfaceClass parent;
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void (*format_statistics)(RdmaProvider *obj, GString *buf);
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};
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#endif
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@@ -37,7 +37,6 @@ void hmp_info_spice(Monitor *mon, const QDict *qdict);
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void hmp_info_balloon(Monitor *mon, const QDict *qdict);
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void hmp_info_irq(Monitor *mon, const QDict *qdict);
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void hmp_info_pic(Monitor *mon, const QDict *qdict);
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void hmp_info_rdma(Monitor *mon, const QDict *qdict);
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void hmp_info_pci(Monitor *mon, const QDict *qdict);
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void hmp_info_tpm(Monitor *mon, const QDict *qdict);
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void hmp_info_iothreads(Monitor *mon, const QDict *qdict);
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File diff suppressed because it is too large
Load Diff
@@ -1,348 +0,0 @@
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/*
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* Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
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*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of EITHER the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation or the BSD
|
||||
* 2-Clause License. This program is distributed in the hope that it
|
||||
* will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
|
||||
* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
|
||||
* See the GNU General Public License version 2 for more details at
|
||||
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program available in the file COPYING in the main
|
||||
* directory of this source tree.
|
||||
*
|
||||
* The BSD 2-Clause License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
||||
* OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#ifndef __PVRDMA_VERBS_H__
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#define __PVRDMA_VERBS_H__
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#include "standard-headers/linux/types.h"
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union pvrdma_gid {
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uint8_t raw[16];
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struct {
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uint64_t subnet_prefix;
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uint64_t interface_id;
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} global;
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};
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enum pvrdma_link_layer {
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PVRDMA_LINK_LAYER_UNSPECIFIED,
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PVRDMA_LINK_LAYER_INFINIBAND,
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PVRDMA_LINK_LAYER_ETHERNET,
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};
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enum pvrdma_mtu {
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PVRDMA_MTU_256 = 1,
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PVRDMA_MTU_512 = 2,
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PVRDMA_MTU_1024 = 3,
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PVRDMA_MTU_2048 = 4,
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PVRDMA_MTU_4096 = 5,
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};
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enum pvrdma_port_state {
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PVRDMA_PORT_NOP = 0,
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PVRDMA_PORT_DOWN = 1,
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PVRDMA_PORT_INIT = 2,
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PVRDMA_PORT_ARMED = 3,
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PVRDMA_PORT_ACTIVE = 4,
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PVRDMA_PORT_ACTIVE_DEFER = 5,
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};
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enum pvrdma_port_cap_flags {
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PVRDMA_PORT_SM = 1 << 1,
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PVRDMA_PORT_NOTICE_SUP = 1 << 2,
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PVRDMA_PORT_TRAP_SUP = 1 << 3,
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PVRDMA_PORT_OPT_IPD_SUP = 1 << 4,
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PVRDMA_PORT_AUTO_MIGR_SUP = 1 << 5,
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PVRDMA_PORT_SL_MAP_SUP = 1 << 6,
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PVRDMA_PORT_MKEY_NVRAM = 1 << 7,
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PVRDMA_PORT_PKEY_NVRAM = 1 << 8,
|
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PVRDMA_PORT_LED_INFO_SUP = 1 << 9,
|
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PVRDMA_PORT_SM_DISABLED = 1 << 10,
|
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PVRDMA_PORT_SYS_IMAGE_GUID_SUP = 1 << 11,
|
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PVRDMA_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12,
|
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PVRDMA_PORT_EXTENDED_SPEEDS_SUP = 1 << 14,
|
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PVRDMA_PORT_CM_SUP = 1 << 16,
|
||||
PVRDMA_PORT_SNMP_TUNNEL_SUP = 1 << 17,
|
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PVRDMA_PORT_REINIT_SUP = 1 << 18,
|
||||
PVRDMA_PORT_DEVICE_MGMT_SUP = 1 << 19,
|
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PVRDMA_PORT_VENDOR_CLASS_SUP = 1 << 20,
|
||||
PVRDMA_PORT_DR_NOTICE_SUP = 1 << 21,
|
||||
PVRDMA_PORT_CAP_MASK_NOTICE_SUP = 1 << 22,
|
||||
PVRDMA_PORT_BOOT_MGMT_SUP = 1 << 23,
|
||||
PVRDMA_PORT_LINK_LATENCY_SUP = 1 << 24,
|
||||
PVRDMA_PORT_CLIENT_REG_SUP = 1 << 25,
|
||||
PVRDMA_PORT_IP_BASED_GIDS = 1 << 26,
|
||||
PVRDMA_PORT_CAP_FLAGS_MAX = PVRDMA_PORT_IP_BASED_GIDS,
|
||||
};
|
||||
|
||||
enum pvrdma_port_width {
|
||||
PVRDMA_WIDTH_1X = 1,
|
||||
PVRDMA_WIDTH_4X = 2,
|
||||
PVRDMA_WIDTH_8X = 4,
|
||||
PVRDMA_WIDTH_12X = 8,
|
||||
};
|
||||
|
||||
enum pvrdma_port_speed {
|
||||
PVRDMA_SPEED_SDR = 1,
|
||||
PVRDMA_SPEED_DDR = 2,
|
||||
PVRDMA_SPEED_QDR = 4,
|
||||
PVRDMA_SPEED_FDR10 = 8,
|
||||
PVRDMA_SPEED_FDR = 16,
|
||||
PVRDMA_SPEED_EDR = 32,
|
||||
};
|
||||
|
||||
struct pvrdma_port_attr {
|
||||
enum pvrdma_port_state state;
|
||||
enum pvrdma_mtu max_mtu;
|
||||
enum pvrdma_mtu active_mtu;
|
||||
uint32_t gid_tbl_len;
|
||||
uint32_t port_cap_flags;
|
||||
uint32_t max_msg_sz;
|
||||
uint32_t bad_pkey_cntr;
|
||||
uint32_t qkey_viol_cntr;
|
||||
uint16_t pkey_tbl_len;
|
||||
uint16_t lid;
|
||||
uint16_t sm_lid;
|
||||
uint8_t lmc;
|
||||
uint8_t max_vl_num;
|
||||
uint8_t sm_sl;
|
||||
uint8_t subnet_timeout;
|
||||
uint8_t init_type_reply;
|
||||
uint8_t active_width;
|
||||
uint8_t active_speed;
|
||||
uint8_t phys_state;
|
||||
uint8_t reserved[2];
|
||||
};
|
||||
|
||||
struct pvrdma_global_route {
|
||||
union pvrdma_gid dgid;
|
||||
uint32_t flow_label;
|
||||
uint8_t sgid_index;
|
||||
uint8_t hop_limit;
|
||||
uint8_t traffic_class;
|
||||
uint8_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_grh {
|
||||
uint32_t version_tclass_flow;
|
||||
uint16_t paylen;
|
||||
uint8_t next_hdr;
|
||||
uint8_t hop_limit;
|
||||
union pvrdma_gid sgid;
|
||||
union pvrdma_gid dgid;
|
||||
};
|
||||
|
||||
enum pvrdma_ah_flags {
|
||||
PVRDMA_AH_GRH = 1,
|
||||
};
|
||||
|
||||
enum pvrdma_rate {
|
||||
PVRDMA_RATE_PORT_CURRENT = 0,
|
||||
PVRDMA_RATE_2_5_GBPS = 2,
|
||||
PVRDMA_RATE_5_GBPS = 5,
|
||||
PVRDMA_RATE_10_GBPS = 3,
|
||||
PVRDMA_RATE_20_GBPS = 6,
|
||||
PVRDMA_RATE_30_GBPS = 4,
|
||||
PVRDMA_RATE_40_GBPS = 7,
|
||||
PVRDMA_RATE_60_GBPS = 8,
|
||||
PVRDMA_RATE_80_GBPS = 9,
|
||||
PVRDMA_RATE_120_GBPS = 10,
|
||||
PVRDMA_RATE_14_GBPS = 11,
|
||||
PVRDMA_RATE_56_GBPS = 12,
|
||||
PVRDMA_RATE_112_GBPS = 13,
|
||||
PVRDMA_RATE_168_GBPS = 14,
|
||||
PVRDMA_RATE_25_GBPS = 15,
|
||||
PVRDMA_RATE_100_GBPS = 16,
|
||||
PVRDMA_RATE_200_GBPS = 17,
|
||||
PVRDMA_RATE_300_GBPS = 18,
|
||||
};
|
||||
|
||||
struct pvrdma_ah_attr {
|
||||
struct pvrdma_global_route grh;
|
||||
uint16_t dlid;
|
||||
uint16_t vlan_id;
|
||||
uint8_t sl;
|
||||
uint8_t src_path_bits;
|
||||
uint8_t static_rate;
|
||||
uint8_t ah_flags;
|
||||
uint8_t port_num;
|
||||
uint8_t dmac[6];
|
||||
uint8_t reserved;
|
||||
};
|
||||
|
||||
enum pvrdma_cq_notify_flags {
|
||||
PVRDMA_CQ_SOLICITED = 1 << 0,
|
||||
PVRDMA_CQ_NEXT_COMP = 1 << 1,
|
||||
PVRDMA_CQ_SOLICITED_MASK = PVRDMA_CQ_SOLICITED |
|
||||
PVRDMA_CQ_NEXT_COMP,
|
||||
PVRDMA_CQ_REPORT_MISSED_EVENTS = 1 << 2,
|
||||
};
|
||||
|
||||
struct pvrdma_qp_cap {
|
||||
uint32_t max_send_wr;
|
||||
uint32_t max_recv_wr;
|
||||
uint32_t max_send_sge;
|
||||
uint32_t max_recv_sge;
|
||||
uint32_t max_inline_data;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
enum pvrdma_sig_type {
|
||||
PVRDMA_SIGNAL_ALL_WR,
|
||||
PVRDMA_SIGNAL_REQ_WR,
|
||||
};
|
||||
|
||||
enum pvrdma_qp_type {
|
||||
PVRDMA_QPT_SMI,
|
||||
PVRDMA_QPT_GSI,
|
||||
PVRDMA_QPT_RC,
|
||||
PVRDMA_QPT_UC,
|
||||
PVRDMA_QPT_UD,
|
||||
PVRDMA_QPT_RAW_IPV6,
|
||||
PVRDMA_QPT_RAW_ETHERTYPE,
|
||||
PVRDMA_QPT_RAW_PACKET = 8,
|
||||
PVRDMA_QPT_XRC_INI = 9,
|
||||
PVRDMA_QPT_XRC_TGT,
|
||||
PVRDMA_QPT_MAX,
|
||||
};
|
||||
|
||||
enum pvrdma_qp_create_flags {
|
||||
PVRDMA_QP_CREATE_IPOPVRDMA_UD_LSO = 1 << 0,
|
||||
PVRDMA_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 1 << 1,
|
||||
};
|
||||
|
||||
enum pvrdma_qp_attr_mask {
|
||||
PVRDMA_QP_STATE = 1 << 0,
|
||||
PVRDMA_QP_CUR_STATE = 1 << 1,
|
||||
PVRDMA_QP_EN_SQD_ASYNC_NOTIFY = 1 << 2,
|
||||
PVRDMA_QP_ACCESS_FLAGS = 1 << 3,
|
||||
PVRDMA_QP_PKEY_INDEX = 1 << 4,
|
||||
PVRDMA_QP_PORT = 1 << 5,
|
||||
PVRDMA_QP_QKEY = 1 << 6,
|
||||
PVRDMA_QP_AV = 1 << 7,
|
||||
PVRDMA_QP_PATH_MTU = 1 << 8,
|
||||
PVRDMA_QP_TIMEOUT = 1 << 9,
|
||||
PVRDMA_QP_RETRY_CNT = 1 << 10,
|
||||
PVRDMA_QP_RNR_RETRY = 1 << 11,
|
||||
PVRDMA_QP_RQ_PSN = 1 << 12,
|
||||
PVRDMA_QP_MAX_QP_RD_ATOMIC = 1 << 13,
|
||||
PVRDMA_QP_ALT_PATH = 1 << 14,
|
||||
PVRDMA_QP_MIN_RNR_TIMER = 1 << 15,
|
||||
PVRDMA_QP_SQ_PSN = 1 << 16,
|
||||
PVRDMA_QP_MAX_DEST_RD_ATOMIC = 1 << 17,
|
||||
PVRDMA_QP_PATH_MIG_STATE = 1 << 18,
|
||||
PVRDMA_QP_CAP = 1 << 19,
|
||||
PVRDMA_QP_DEST_QPN = 1 << 20,
|
||||
PVRDMA_QP_ATTR_MASK_MAX = PVRDMA_QP_DEST_QPN,
|
||||
};
|
||||
|
||||
enum pvrdma_qp_state {
|
||||
PVRDMA_QPS_RESET,
|
||||
PVRDMA_QPS_INIT,
|
||||
PVRDMA_QPS_RTR,
|
||||
PVRDMA_QPS_RTS,
|
||||
PVRDMA_QPS_SQD,
|
||||
PVRDMA_QPS_SQE,
|
||||
PVRDMA_QPS_ERR,
|
||||
};
|
||||
|
||||
enum pvrdma_mig_state {
|
||||
PVRDMA_MIG_MIGRATED,
|
||||
PVRDMA_MIG_REARM,
|
||||
PVRDMA_MIG_ARMED,
|
||||
};
|
||||
|
||||
enum pvrdma_mw_type {
|
||||
PVRDMA_MW_TYPE_1 = 1,
|
||||
PVRDMA_MW_TYPE_2 = 2,
|
||||
};
|
||||
|
||||
struct pvrdma_srq_attr {
|
||||
uint32_t max_wr;
|
||||
uint32_t max_sge;
|
||||
uint32_t srq_limit;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_qp_attr {
|
||||
enum pvrdma_qp_state qp_state;
|
||||
enum pvrdma_qp_state cur_qp_state;
|
||||
enum pvrdma_mtu path_mtu;
|
||||
enum pvrdma_mig_state path_mig_state;
|
||||
uint32_t qkey;
|
||||
uint32_t rq_psn;
|
||||
uint32_t sq_psn;
|
||||
uint32_t dest_qp_num;
|
||||
uint32_t qp_access_flags;
|
||||
uint16_t pkey_index;
|
||||
uint16_t alt_pkey_index;
|
||||
uint8_t en_sqd_async_notify;
|
||||
uint8_t sq_draining;
|
||||
uint8_t max_rd_atomic;
|
||||
uint8_t max_dest_rd_atomic;
|
||||
uint8_t min_rnr_timer;
|
||||
uint8_t port_num;
|
||||
uint8_t timeout;
|
||||
uint8_t retry_cnt;
|
||||
uint8_t rnr_retry;
|
||||
uint8_t alt_port_num;
|
||||
uint8_t alt_timeout;
|
||||
uint8_t reserved[5];
|
||||
struct pvrdma_qp_cap cap;
|
||||
struct pvrdma_ah_attr ah_attr;
|
||||
struct pvrdma_ah_attr alt_ah_attr;
|
||||
};
|
||||
|
||||
enum pvrdma_send_flags {
|
||||
PVRDMA_SEND_FENCE = 1 << 0,
|
||||
PVRDMA_SEND_SIGNALED = 1 << 1,
|
||||
PVRDMA_SEND_SOLICITED = 1 << 2,
|
||||
PVRDMA_SEND_INLINE = 1 << 3,
|
||||
PVRDMA_SEND_IP_CSUM = 1 << 4,
|
||||
PVRDMA_SEND_FLAGS_MAX = PVRDMA_SEND_IP_CSUM,
|
||||
};
|
||||
|
||||
enum pvrdma_access_flags {
|
||||
PVRDMA_ACCESS_LOCAL_WRITE = 1 << 0,
|
||||
PVRDMA_ACCESS_REMOTE_WRITE = 1 << 1,
|
||||
PVRDMA_ACCESS_REMOTE_READ = 1 << 2,
|
||||
PVRDMA_ACCESS_REMOTE_ATOMIC = 1 << 3,
|
||||
PVRDMA_ACCESS_MW_BIND = 1 << 4,
|
||||
PVRDMA_ZERO_BASED = 1 << 5,
|
||||
PVRDMA_ACCESS_ON_DEMAND = 1 << 6,
|
||||
PVRDMA_ACCESS_FLAGS_MAX = PVRDMA_ACCESS_ON_DEMAND,
|
||||
};
|
||||
|
||||
#endif /* __PVRDMA_VERBS_H__ */
|
||||
@@ -1,310 +0,0 @@
|
||||
/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of EITHER the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation or the BSD
|
||||
* 2-Clause License. This program is distributed in the hope that it
|
||||
* will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
|
||||
* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
|
||||
* See the GNU General Public License version 2 for more details at
|
||||
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program available in the file COPYING in the main
|
||||
* directory of this source tree.
|
||||
*
|
||||
* The BSD 2-Clause License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
||||
* OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __VMW_PVRDMA_ABI_H__
|
||||
#define __VMW_PVRDMA_ABI_H__
|
||||
|
||||
#include "standard-headers/linux/types.h"
|
||||
|
||||
#define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */
|
||||
#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */
|
||||
#define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */
|
||||
#define PVRDMA_UAR_QP_SEND (1 << 30) /* Send bit. */
|
||||
#define PVRDMA_UAR_QP_RECV (1 << 31) /* Recv bit. */
|
||||
#define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */
|
||||
#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) /* Arm solicited bit. */
|
||||
#define PVRDMA_UAR_CQ_ARM (1 << 30) /* Arm bit. */
|
||||
#define PVRDMA_UAR_CQ_POLL (1 << 31) /* Poll bit. */
|
||||
#define PVRDMA_UAR_SRQ_OFFSET 8 /* SRQ doorbell. */
|
||||
#define PVRDMA_UAR_SRQ_RECV (1 << 30) /* Recv bit. */
|
||||
|
||||
enum pvrdma_wr_opcode {
|
||||
PVRDMA_WR_RDMA_WRITE,
|
||||
PVRDMA_WR_RDMA_WRITE_WITH_IMM,
|
||||
PVRDMA_WR_SEND,
|
||||
PVRDMA_WR_SEND_WITH_IMM,
|
||||
PVRDMA_WR_RDMA_READ,
|
||||
PVRDMA_WR_ATOMIC_CMP_AND_SWP,
|
||||
PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
|
||||
PVRDMA_WR_LSO,
|
||||
PVRDMA_WR_SEND_WITH_INV,
|
||||
PVRDMA_WR_RDMA_READ_WITH_INV,
|
||||
PVRDMA_WR_LOCAL_INV,
|
||||
PVRDMA_WR_FAST_REG_MR,
|
||||
PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
|
||||
PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
|
||||
PVRDMA_WR_BIND_MW,
|
||||
PVRDMA_WR_REG_SIG_MR,
|
||||
PVRDMA_WR_ERROR,
|
||||
};
|
||||
|
||||
enum pvrdma_wc_status {
|
||||
PVRDMA_WC_SUCCESS,
|
||||
PVRDMA_WC_LOC_LEN_ERR,
|
||||
PVRDMA_WC_LOC_QP_OP_ERR,
|
||||
PVRDMA_WC_LOC_EEC_OP_ERR,
|
||||
PVRDMA_WC_LOC_PROT_ERR,
|
||||
PVRDMA_WC_WR_FLUSH_ERR,
|
||||
PVRDMA_WC_MW_BIND_ERR,
|
||||
PVRDMA_WC_BAD_RESP_ERR,
|
||||
PVRDMA_WC_LOC_ACCESS_ERR,
|
||||
PVRDMA_WC_REM_INV_REQ_ERR,
|
||||
PVRDMA_WC_REM_ACCESS_ERR,
|
||||
PVRDMA_WC_REM_OP_ERR,
|
||||
PVRDMA_WC_RETRY_EXC_ERR,
|
||||
PVRDMA_WC_RNR_RETRY_EXC_ERR,
|
||||
PVRDMA_WC_LOC_RDD_VIOL_ERR,
|
||||
PVRDMA_WC_REM_INV_RD_REQ_ERR,
|
||||
PVRDMA_WC_REM_ABORT_ERR,
|
||||
PVRDMA_WC_INV_EECN_ERR,
|
||||
PVRDMA_WC_INV_EEC_STATE_ERR,
|
||||
PVRDMA_WC_FATAL_ERR,
|
||||
PVRDMA_WC_RESP_TIMEOUT_ERR,
|
||||
PVRDMA_WC_GENERAL_ERR,
|
||||
};
|
||||
|
||||
enum pvrdma_wc_opcode {
|
||||
PVRDMA_WC_SEND,
|
||||
PVRDMA_WC_RDMA_WRITE,
|
||||
PVRDMA_WC_RDMA_READ,
|
||||
PVRDMA_WC_COMP_SWAP,
|
||||
PVRDMA_WC_FETCH_ADD,
|
||||
PVRDMA_WC_BIND_MW,
|
||||
PVRDMA_WC_LSO,
|
||||
PVRDMA_WC_LOCAL_INV,
|
||||
PVRDMA_WC_FAST_REG_MR,
|
||||
PVRDMA_WC_MASKED_COMP_SWAP,
|
||||
PVRDMA_WC_MASKED_FETCH_ADD,
|
||||
PVRDMA_WC_RECV = 1 << 7,
|
||||
PVRDMA_WC_RECV_RDMA_WITH_IMM,
|
||||
};
|
||||
|
||||
enum pvrdma_wc_flags {
|
||||
PVRDMA_WC_GRH = 1 << 0,
|
||||
PVRDMA_WC_WITH_IMM = 1 << 1,
|
||||
PVRDMA_WC_WITH_INVALIDATE = 1 << 2,
|
||||
PVRDMA_WC_IP_CSUM_OK = 1 << 3,
|
||||
PVRDMA_WC_WITH_SMAC = 1 << 4,
|
||||
PVRDMA_WC_WITH_VLAN = 1 << 5,
|
||||
PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6,
|
||||
PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE,
|
||||
};
|
||||
|
||||
enum pvrdma_network_type {
|
||||
PVRDMA_NETWORK_IB,
|
||||
PVRDMA_NETWORK_ROCE_V1 = PVRDMA_NETWORK_IB,
|
||||
PVRDMA_NETWORK_IPV4,
|
||||
PVRDMA_NETWORK_IPV6
|
||||
};
|
||||
|
||||
struct pvrdma_alloc_ucontext_resp {
|
||||
uint32_t qp_tab_size;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_alloc_pd_resp {
|
||||
uint32_t pdn;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_create_cq {
|
||||
uint64_t __attribute__((aligned(8))) buf_addr;
|
||||
uint32_t buf_size;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_create_cq_resp {
|
||||
uint32_t cqn;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_resize_cq {
|
||||
uint64_t __attribute__((aligned(8))) buf_addr;
|
||||
uint32_t buf_size;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_create_srq {
|
||||
uint64_t __attribute__((aligned(8))) buf_addr;
|
||||
uint32_t buf_size;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_create_srq_resp {
|
||||
uint32_t srqn;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
struct pvrdma_create_qp {
|
||||
uint64_t __attribute__((aligned(8))) rbuf_addr;
|
||||
uint64_t __attribute__((aligned(8))) sbuf_addr;
|
||||
uint32_t rbuf_size;
|
||||
uint32_t sbuf_size;
|
||||
uint64_t __attribute__((aligned(8))) qp_addr;
|
||||
};
|
||||
|
||||
struct pvrdma_create_qp_resp {
|
||||
uint32_t qpn;
|
||||
uint32_t qp_handle;
|
||||
};
|
||||
|
||||
/* PVRDMA masked atomic compare and swap */
|
||||
struct pvrdma_ex_cmp_swap {
|
||||
uint64_t __attribute__((aligned(8))) swap_val;
|
||||
uint64_t __attribute__((aligned(8))) compare_val;
|
||||
uint64_t __attribute__((aligned(8))) swap_mask;
|
||||
uint64_t __attribute__((aligned(8))) compare_mask;
|
||||
};
|
||||
|
||||
/* PVRDMA masked atomic fetch and add */
|
||||
struct pvrdma_ex_fetch_add {
|
||||
uint64_t __attribute__((aligned(8))) add_val;
|
||||
uint64_t __attribute__((aligned(8))) field_boundary;
|
||||
};
|
||||
|
||||
/* PVRDMA address vector. */
|
||||
struct pvrdma_av {
|
||||
uint32_t port_pd;
|
||||
uint32_t sl_tclass_flowlabel;
|
||||
uint8_t dgid[16];
|
||||
uint8_t src_path_bits;
|
||||
uint8_t gid_index;
|
||||
uint8_t stat_rate;
|
||||
uint8_t hop_limit;
|
||||
uint8_t dmac[6];
|
||||
uint8_t reserved[6];
|
||||
};
|
||||
|
||||
/* PVRDMA scatter/gather entry */
|
||||
struct pvrdma_sge {
|
||||
uint64_t __attribute__((aligned(8))) addr;
|
||||
uint32_t length;
|
||||
uint32_t lkey;
|
||||
};
|
||||
|
||||
/* PVRDMA receive queue work request */
|
||||
struct pvrdma_rq_wqe_hdr {
|
||||
uint64_t __attribute__((aligned(8))) wr_id; /* wr id */
|
||||
uint32_t num_sge; /* size of s/g array */
|
||||
uint32_t total_len; /* reserved */
|
||||
};
|
||||
/* Use pvrdma_sge (ib_sge) for receive queue s/g array elements. */
|
||||
|
||||
/* PVRDMA send queue work request */
|
||||
struct pvrdma_sq_wqe_hdr {
|
||||
uint64_t __attribute__((aligned(8))) wr_id; /* wr id */
|
||||
uint32_t num_sge; /* size of s/g array */
|
||||
uint32_t total_len; /* reserved */
|
||||
uint32_t opcode; /* operation type */
|
||||
uint32_t send_flags; /* wr flags */
|
||||
union {
|
||||
uint32_t imm_data;
|
||||
uint32_t invalidate_rkey;
|
||||
} ex;
|
||||
uint32_t reserved;
|
||||
union {
|
||||
struct {
|
||||
uint64_t __attribute__((aligned(8))) remote_addr;
|
||||
uint32_t rkey;
|
||||
uint8_t reserved[4];
|
||||
} rdma;
|
||||
struct {
|
||||
uint64_t __attribute__((aligned(8))) remote_addr;
|
||||
uint64_t __attribute__((aligned(8))) compare_add;
|
||||
uint64_t __attribute__((aligned(8))) swap;
|
||||
uint32_t rkey;
|
||||
uint32_t reserved;
|
||||
} atomic;
|
||||
struct {
|
||||
uint64_t __attribute__((aligned(8))) remote_addr;
|
||||
uint32_t log_arg_sz;
|
||||
uint32_t rkey;
|
||||
union {
|
||||
struct pvrdma_ex_cmp_swap cmp_swap;
|
||||
struct pvrdma_ex_fetch_add fetch_add;
|
||||
} wr_data;
|
||||
} masked_atomics;
|
||||
struct {
|
||||
uint64_t __attribute__((aligned(8))) iova_start;
|
||||
uint64_t __attribute__((aligned(8))) pl_pdir_dma;
|
||||
uint32_t page_shift;
|
||||
uint32_t page_list_len;
|
||||
uint32_t length;
|
||||
uint32_t access_flags;
|
||||
uint32_t rkey;
|
||||
uint32_t reserved;
|
||||
} fast_reg;
|
||||
struct {
|
||||
uint32_t remote_qpn;
|
||||
uint32_t remote_qkey;
|
||||
struct pvrdma_av av;
|
||||
} ud;
|
||||
} wr;
|
||||
};
|
||||
/* Use pvrdma_sge (ib_sge) for send queue s/g array elements. */
|
||||
|
||||
/* Completion queue element. */
|
||||
struct pvrdma_cqe {
|
||||
uint64_t __attribute__((aligned(8))) wr_id;
|
||||
uint64_t __attribute__((aligned(8))) qp;
|
||||
uint32_t opcode;
|
||||
uint32_t status;
|
||||
uint32_t byte_len;
|
||||
uint32_t imm_data;
|
||||
uint32_t src_qp;
|
||||
uint32_t wc_flags;
|
||||
uint32_t vendor_err;
|
||||
uint16_t pkey_index;
|
||||
uint16_t slid;
|
||||
uint8_t sl;
|
||||
uint8_t dlid_path_bits;
|
||||
uint8_t port_num;
|
||||
uint8_t smac[6];
|
||||
uint8_t network_hdr_type;
|
||||
uint8_t reserved2[6]; /* Pad to next power of 2 (64). */
|
||||
};
|
||||
|
||||
#endif /* __VMW_PVRDMA_ABI_H__ */
|
||||
@@ -18,7 +18,6 @@ enum {
|
||||
QEMU_ARCH_XTENSA = (1 << 12),
|
||||
QEMU_ARCH_OPENRISC = (1 << 13),
|
||||
QEMU_ARCH_TRICORE = (1 << 16),
|
||||
QEMU_ARCH_NIOS2 = (1 << 17),
|
||||
QEMU_ARCH_HPPA = (1 << 18),
|
||||
QEMU_ARCH_RISCV = (1 << 19),
|
||||
QEMU_ARCH_RX = (1 << 20),
|
||||
|
||||
Reference in New Issue
Block a user