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i386: Helpers to encode cache information consistently

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Instead of having a collection of macros that need to be used in
complex expressions to build CPUID data, define a CPUCacheInfo
struct that can hold information about a given cache.  Helper
functions will take a CPUCacheInfo struct as input to encode
CPUID leaves for a cache.

This will help us ensure consistency between cache information
CPUID leaves, and make the existing inconsistencies in CPUID info
more visible.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
Message-Id: <20180510204148.11687-2-babu.moger@amd.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Eduardo Habkost
2018-05-15 11:33:33 -03:00
parent 0da0fb0628
commit 7e3482f824
2 changed files with 424 additions and 124 deletions
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target/i386/cpu.c
+371 -124
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File diff suppressed because it is too large Load Diff
target/i386/cpu.h
+53
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@@ -1045,6 +1045,59 @@ typedef enum TPRAccess {
TPR_ACCESS_WRITE,
} TPRAccess;
/* Cache information data structures: */
enum CacheType {
DCACHE,
ICACHE,
UNIFIED_CACHE
};
typedef struct CPUCacheInfo {
enum CacheType type;
uint8_t level;
/* Size in bytes */
uint32_t size;
/* Line size, in bytes */
uint16_t line_size;
/*
* Associativity.
* Note: representation of fully-associative caches is not implemented
*/
uint8_t associativity;
/* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
uint8_t partitions;
/* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
uint32_t sets;
/*
* Lines per tag.
* AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
* (Is this synonym to @partitions?)
*/
uint8_t lines_per_tag;
/* Self-initializing cache */
bool self_init;
/*
* WBINVD/INVD is not guaranteed to act upon lower level caches of
* non-originating threads sharing this cache.
* CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
*/
bool no_invd_sharing;
/*
* Cache is inclusive of lower cache levels.
* CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
*/
bool inclusive;
/*
* A complex function is used to index the cache, potentially using all
* address bits. CPUID[4].EDX[bit 2].
*/
bool complex_indexing;
} CPUCacheInfo;
typedef struct CPUX86State {
/* standard registers */
target_ulong regs[CPU_NB_REGS];