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cpu: Move cpu_index field to CPUState

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Note that target-alpha accesses this field from TCG, now using a
negative offset. Therefore the field is placed last in CPUState.

Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.

Move common parts of mips cpu_state_reset() to mips_cpu_reset().

Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
[AF: Rebased onto ppc CPU subclasses and openpic changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber
2013-01-15 04:09:13 +01:00
parent 1b1ed8dc40
commit 55e5c28502
40 changed files with 153 additions and 102 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cpus.c
+9 -5
View File
@@ -390,13 +390,15 @@ void hw_error(const char *fmt, ...)
{
va_list ap;
CPUArchState *env;
CPUState *cpu;
va_start(ap, fmt);
fprintf(stderr, "qemu: hardware error: ");
vfprintf(stderr, fmt, ap);
fprintf(stderr, "\n");
for(env = first_cpu; env != NULL; env = env->next_cpu) {
fprintf(stderr, "CPU #%d:\n", env->cpu_index);
for (env = first_cpu; env != NULL; env = env->next_cpu) {
cpu = ENV_GET_CPU(env);
fprintf(stderr, "CPU #%d:\n", cpu->cpu_index);
cpu_dump_state(env, stderr, fprintf, CPU_DUMP_FPU);
}
va_end(ap);
@@ -1166,7 +1168,7 @@ void set_numa_modes(void)
for (env = first_cpu; env != NULL; env = env->next_cpu) {
cpu = ENV_GET_CPU(env);
for (i = 0; i < nb_numa_nodes; i++) {
if (test_bit(env->cpu_index, node_cpumask[i])) {
if (test_bit(cpu->cpu_index, node_cpumask[i])) {
cpu->numa_node = i;
}
}
@@ -1215,7 +1217,7 @@ CpuInfoList *qmp_query_cpus(Error **errp)
info = g_malloc0(sizeof(*info));
info->value = g_malloc0(sizeof(*info->value));
info->value->CPU = env->cpu_index;
info->value->CPU = cpu->cpu_index;
info->value->current = (env == first_cpu);
info->value->halted = env->halted;
info->value->thread_id = cpu->thread_id;
@@ -1253,6 +1255,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
FILE *f;
uint32_t l;
CPUArchState *env;
CPUState *cpu;
uint8_t buf[1024];
if (!has_cpu) {
@@ -1260,7 +1263,8 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
}
for (env = first_cpu; env; env = env->next_cpu) {
if (cpu_index == env->cpu_index) {
cpu = ENV_GET_CPU(env);
if (cpu_index == cpu->cpu_index) {
break;
}
}
exec.c
+7 -6
View File
@@ -247,13 +247,16 @@ static const VMStateDescription vmstate_cpu_common = {
};
#endif
CPUArchState *qemu_get_cpu(int cpu)
CPUArchState *qemu_get_cpu(int index)
{
CPUArchState *env = first_cpu;
CPUState *cpu;
while (env) {
if (env->cpu_index == cpu)
cpu = ENV_GET_CPU(env);
if (cpu->cpu_index == index) {
break;
}
env = env->next_cpu;
}
@@ -276,7 +279,7 @@ void cpu_exec_init(CPUArchState *env)
penv = &(*penv)->next_cpu;
cpu_index++;
}
env->cpu_index = cpu_index;
cpu->cpu_index = cpu_index;
cpu->numa_node = 0;
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
@@ -529,7 +532,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
{
CPUArchState *new_env = cpu_init(env->cpu_model_str);
CPUArchState *next_cpu = new_env->next_cpu;
int cpu_index = new_env->cpu_index;
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
CPUWatchpoint *wp;
@@ -537,9 +539,8 @@ CPUArchState *cpu_copy(CPUArchState *env)
memcpy(new_env, env, sizeof(CPUArchState));
/* Preserve chaining and index. */
/* Preserve chaining. */
new_env->next_cpu = next_cpu;
new_env->cpu_index = cpu_index;
/* Clone all break/watchpoints.
Note: Once we support ptrace with hw-debug register access, make sure
gdbstub.c
+2 -1
View File
@@ -2401,9 +2401,10 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
thread = strtoull(p+16, (char **)&p, 16);
env = find_cpu(thread);
if (env != NULL) {
CPUState *cpu = ENV_GET_CPU(env);
cpu_synchronize_state(env);
len = snprintf((char *)mem_buf, sizeof(mem_buf),
"CPU#%d [%s]", env->cpu_index,
"CPU#%d [%s]", cpu->cpu_index,
env->halted ? "halted " : "running");
memtohex(buf, mem_buf, len);
put_packet(s, buf);
hw/alpha_typhoon.c
+3 -1
View File
@@ -75,6 +75,7 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
{
CPUAlphaState *env = cpu_single_env;
TyphoonState *s = opaque;
CPUState *cpu;
uint64_t ret = 0;
if (addr & 4) {
@@ -95,7 +96,8 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
case 0x0080:
/* MISC: Miscellaneous Register. */
ret = s->cchip.misc | (env->cpu_index & 3);
cpu = ENV_GET_CPU(env);
ret = s->cchip.misc | (cpu->cpu_index & 3);
break;
case 0x00c0:
hw/arm_gic.c
+2 -1
View File
@@ -39,7 +39,8 @@ static const uint8_t gic_id[] = {
static inline int gic_get_current_cpu(GICState *s)
{
if (s->num_cpu > 1) {
return cpu_single_env->cpu_index;
CPUState *cpu = ENV_GET_CPU(cpu_single_env);
return cpu->cpu_index;
}
return 0;
}
hw/arm_mptimer.c
+5 -3
View File
@@ -49,11 +49,13 @@ typedef struct {
static inline int get_current_cpu(arm_mptimer_state *s)
{
if (cpu_single_env->cpu_index >= s->num_cpu) {
CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
if (cpu_single_cpu->cpu_index >= s->num_cpu) {
hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
s->num_cpu, cpu_single_env->cpu_index);
s->num_cpu, cpu_single_cpu->cpu_index);
}
return cpu_single_env->cpu_index;
return cpu_single_cpu->cpu_index;
}
static inline void timerblock_update_irq(timerblock *tb)
hw/openpic.c
+4 -1
View File
@@ -153,11 +153,14 @@ static const int debug_openpic = 0;
static int get_current_cpu(void)
{
CPUState *cpu_single_cpu;
if (!cpu_single_env) {
return -1;
}
return cpu_single_env->cpu_index;
cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
return cpu_single_cpu->cpu_index;
}
static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
hw/ppc/e500.c
+11 -6
View File
@@ -239,25 +239,28 @@ static int ppce500_load_device_tree(CPUPPCState *env,
/* We need to generate the cpu nodes in reverse order, so Linux can pick
the first node as boot node and be happy */
for (i = smp_cpus - 1; i >= 0; i--) {
CPUState *cpu = NULL;
char cpu_name[128];
uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (env->cpu_index == i) {
cpu = ENV_GET_CPU(env);
if (cpu->cpu_index == i) {
break;
}
}
if (!env) {
if (cpu == NULL) {
continue;
}
snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
cpu->cpu_index);
qemu_devtree_add_subnode(fdt, cpu_name);
qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index);
qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
env->dcache_line_size);
qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
@@ -265,7 +268,7 @@ static int ppce500_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
if (env->cpu_index) {
if (cpu->cpu_index) {
qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
@@ -479,6 +482,7 @@ void ppce500_init(PPCE500Params *params)
irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
for (i = 0; i < smp_cpus; i++) {
PowerPCCPU *cpu;
CPUState *cs;
qemu_irq *input;
cpu = cpu_ppc_init(params->cpu_model);
@@ -487,6 +491,7 @@ void ppce500_init(PPCE500Params *params)
exit(1);
}
env = &cpu->env;
cs = CPU(cpu);
if (!firstenv) {
firstenv = env;
@@ -496,7 +501,7 @@ void ppce500_init(PPCE500Params *params)
input = (qemu_irq *)env->irq_inputs;
irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i;
env->mpic_iack = MPC8544_CCSRBAR_BASE +
MPC8544_MPIC_REGS_OFFSET + 0x200A0;
hw/ppce500_spin.c
+5 -3
View File
@@ -124,21 +124,23 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value,
SpinState *s = opaque;
int env_idx = addr / sizeof(SpinInfo);
CPUPPCState *env;
CPUState *cpu = NULL;
SpinInfo *curspin = &s->spin[env_idx];
uint8_t *curspin_p = (uint8_t*)curspin;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (env->cpu_index == env_idx) {
cpu = CPU(ppc_env_get_cpu(env));
if (cpu->cpu_index == env_idx) {
break;
}
}
if (!env) {
if (cpu == NULL) {
/* Unknown CPU */
return;
}
if (!env->cpu_index) {
if (cpu->cpu_index == 0) {
/* primary CPU doesn't spin */
return;
}
hw/pxa.h
+1 -1
View File
@@ -69,7 +69,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUARMState *env, DeviceState *pic, int lines);
ARMCPU *cpu, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
hw/pxa2xx.c
+2 -2
View File
@@ -2045,7 +2045,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
NULL);
s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 121);
s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
dinfo = drive_get(IF_SD, 0, 0);
if (!dinfo) {
@@ -2176,7 +2176,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
NULL);
s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 85);
s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
dinfo = drive_get(IF_SD, 0, 0);
if (!dinfo) {
hw/pxa2xx_gpio.c
+3 -2
View File
@@ -250,13 +250,14 @@ static const MemoryRegionOps pxa_gpio_ops = {
};
DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUARMState *env, DeviceState *pic, int lines)
ARMCPU *cpu, DeviceState *pic, int lines)
{
CPUState *cs = CPU(cpu);
DeviceState *dev;
dev = qdev_create(NULL, "pxa2xx-gpio");
qdev_prop_set_int32(dev, "lines", lines);
qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
hw/spapr.c
+6 -5
View File
@@ -148,20 +148,20 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr)
assert(spapr->cpu_model);
for (env = first_cpu; env != NULL; env = env->next_cpu) {
cpu = ENV_GET_CPU(env);
cpu = CPU(ppc_env_get_cpu(env));
uint32_t associativity[] = {cpu_to_be32(0x5),
cpu_to_be32(0x0),
cpu_to_be32(0x0),
cpu_to_be32(0x0),
cpu_to_be32(cpu->numa_node),
cpu_to_be32(env->cpu_index)};
cpu_to_be32(cpu->cpu_index)};
if ((env->cpu_index % smt) != 0) {
if ((cpu->cpu_index % smt) != 0) {
continue;
}
snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model,
env->cpu_index);
cpu->cpu_index);
offset = fdt_path_offset(fdt, cpu_model);
if (offset < 0) {
@@ -310,7 +310,8 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
spapr->cpu_model = g_strdup(modelname);
for (env = first_cpu; env != NULL; env = env->next_cpu) {
int index = env->cpu_index;
CPUState *cpu = CPU(ppc_env_get_cpu(env));
int index = cpu->cpu_index;
uint32_t servers_prop[smp_threads];
uint32_t gservers_prop[smp_threads * 2];
char *nodename;
hw/spapr_hcall.c
+3 -1
View File
@@ -467,9 +467,11 @@ static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong vpa = args[2];
target_ulong ret = H_PARAMETER;
CPUPPCState *tenv;
CPUState *tcpu;
for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
if (tenv->cpu_index == procno) {
tcpu = CPU(ppc_env_get_cpu(tenv));
if (tcpu->cpu_index == procno) {
break;
}
}
hw/spapr_rtas.c
+5 -3
View File
@@ -131,6 +131,7 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr,
{
target_ulong id;
CPUPPCState *env;
CPUState *cpu;
if (nargs != 1 || nret != 2) {
rtas_st(rets, 0, -3);
@@ -139,7 +140,8 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr,
id = rtas_ld(args, 0);
for (env = first_cpu; env; env = env->next_cpu) {
if (env->cpu_index != id) {
cpu = CPU(ppc_env_get_cpu(env));
if (cpu->cpu_index != id) {
continue;
}
@@ -176,9 +178,9 @@ static void rtas_start_cpu(sPAPREnvironment *spapr,
r3 = rtas_ld(args, 2);
for (env = first_cpu; env; env = env->next_cpu) {
cpu = ENV_GET_CPU(env);
cpu = CPU(ppc_env_get_cpu(env));
if (env->cpu_index != id) {
if (cpu->cpu_index != id) {
continue;
}
hw/xics.c
+12 -10
View File
@@ -357,10 +357,10 @@ void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
CPUPPCState *env = &cpu->env;
CPUState *cs = CPU(cpu);
target_ulong cppr = args[0];
icp_set_cppr(spapr->icp, env->cpu_index, cppr);
icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
return H_SUCCESS;
}
@@ -376,14 +376,13 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
icp_set_mfrr(spapr->icp, server, mfrr);
return H_SUCCESS;
}
static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
CPUPPCState *env = &cpu->env;
uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);
CPUState *cs = CPU(cpu);
uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
args[0] = xirr;
return H_SUCCESS;
@@ -392,10 +391,10 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
CPUPPCState *env = &cpu->env;
CPUState *cs = CPU(cpu);
target_ulong xirr = args[0];
icp_eoi(spapr->icp, env->cpu_index, xirr);
icp_eoi(spapr->icp, cs->cpu_index, xirr);
return H_SUCCESS;
}
@@ -525,14 +524,16 @@ static void xics_reset(void *opaque)
struct icp_state *xics_system_init(int nr_irqs)
{
CPUPPCState *env;
CPUState *cpu;
int max_server_num;
struct icp_state *icp;
struct ics_state *ics;
max_server_num = -1;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (env->cpu_index > max_server_num) {
max_server_num = env->cpu_index;
cpu = CPU(ppc_env_get_cpu(env));
if (cpu->cpu_index > max_server_num) {
max_server_num = cpu->cpu_index;
}
}
@@ -541,7 +542,8 @@ struct icp_state *xics_system_init(int nr_irqs)
icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
for (env = first_cpu; env != NULL; env = env->next_cpu) {
struct icp_server_state *ss = &icp->ss[env->cpu_index];
cpu = CPU(ppc_env_get_cpu(env));
struct icp_server_state *ss = &icp->ss[cpu->cpu_index];
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER7:
include/exec/cpu-defs.h
-1
View File
@@ -193,7 +193,6 @@ typedef struct CPUWatchpoint {
int exception_index; \
\
CPUArchState *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
uint32_t host_tid; /* host thread ID */ \
int running; /* Nonzero if cpu is currently running(usermode). */ \
/* user data */ \
include/exec/gdbstub.h
+2 -1
View File
@@ -35,7 +35,8 @@ static inline int cpu_index(CPUArchState *env)
#if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
return env->host_tid;
#else
return env->cpu_index + 1;
CPUState *cpu = ENV_GET_CPU(env);
return cpu->cpu_index + 1;
#endif
}
include/qom/cpu.h
+2
View File
@@ -57,6 +57,7 @@ struct kvm_run;
/**
* CPUState:
* @cpu_index: CPU index (informative).
* @nr_cores: Number of cores within this CPU package.
* @nr_threads: Number of threads within this CPU.
* @numa_node: NUMA node this CPU is belonging to.
@@ -96,6 +97,7 @@ struct CPUState {
struct kvm_run *kvm_run;
/* TODO Move common fields from CPUArchState here. */
int cpu_index; /* used by alpha TCG */
};
kvm-all.c
+1 -1
View File
@@ -223,7 +223,7 @@ int kvm_init_vcpu(CPUArchState *env)
DPRINTF("kvm_init_vcpu\n");
ret = kvm_vm_ioctl(s, KVM_CREATE_VCPU, env->cpu_index);
ret = kvm_vm_ioctl(s, KVM_CREATE_VCPU, cpu->cpu_index);
if (ret < 0) {
DPRINTF("kvm_create_vcpu failed\n");
goto err;

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