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target/cris: Remove the deprecated CRIS target

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The CRIS target is deprecated since v9.0 (commit c7bbef4023
"docs: mark CRIS support as deprecated").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-ID: <20240904143603.52934-14-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2024-09-13 20:11:13 +02:00
parent 01d01edc9f
commit 44e4075bf4
29 changed files with 9 additions and 7306 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
-1
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@@ -227,7 +227,6 @@ F: tests/functional/test_avr_mega2560.py
CRIS TCG CPUs
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
S: Maintained
F: target/cris/
F: disas/cris.c
Hexagon TCG CPUs
docs/about/deprecated.rst
-8
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@@ -206,14 +206,6 @@ in the QEMU object model anymore. ``Sun-UltraSparc-IIIi+`` and
but for consistency these will get removed in a future release, too.
Use ``Sun-UltraSparc-IIIi-plus`` and ``Sun-UltraSparc-IV-plus`` instead.
CRIS CPU architecture (since 9.0)
'''''''''''''''''''''''''''''''''
The CRIS architecture was pulled from Linux in 4.17 and the compiler
is no longer packaged in any distro making it harder to run the
``check-tcg`` tests. Unless we can improve the testing situation there
is a chance the code will bitrot without anyone noticing.
System emulator machines
------------------------
docs/about/emulation.rst
-4
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@@ -26,10 +26,6 @@ depending on the guest architecture.
- :ref:`Yes<AVR-System-emulator>`
- No
- 8 bit micro controller, often used in maker projects
* - Cris
- Yes
- Yes
- Embedded RISC chip developed by AXIS
* - Hexagon
- No
- Yes
docs/about/removed-features.rst
+7
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@@ -889,6 +889,13 @@ Nios II CPU (removed in 9.1)
QEMU Nios II architecture was orphan; Intel has EOL'ed the Nios II
processor IP (see `Intel discontinuance notification`_).
CRIS CPU architecture (removed in 9.2)
''''''''''''''''''''''''''''''''''''''
The CRIS architecture was pulled from Linux in 4.17 and the compiler
was no longer packaged in any distro making it harder to run the
``check-tcg`` tests.
System accelerators
-------------------
fpu/softfloat-specialize.c.inc
+2 -2
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@@ -151,8 +151,8 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
#else
/*
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
* S390, SH4, TriCore, and Xtensa. Our other supported targets,
* such CRIS, do not have floating-point.
* S390, SH4, TriCore, and Xtensa. Our other supported targets
* do not have floating-point.
*/
if (snan_bit_is_one(status)) {
/* set all bits other than msb */
include/exec/poison.h
-1
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@@ -11,7 +11,6 @@
#pragma GCC poison TARGET_AARCH64
#pragma GCC poison TARGET_ALPHA
#pragma GCC poison TARGET_ARM
#pragma GCC poison TARGET_CRIS
#pragma GCC poison TARGET_HEXAGON
#pragma GCC poison TARGET_HPPA
#pragma GCC poison TARGET_LOONGARCH64
scripts/coverity-scan/COMPONENTS.md
-3
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@@ -9,9 +9,6 @@ arm
avr
~ .*/qemu((/include)?/hw/avr/.*|/target/avr/.*)
cris
~ .*/qemu/target/cris/.*
hexagon-gen (component should be ignored in analysis)
~ .*/qemu(/target/hexagon/.*generated.*)
target/Kconfig
-1
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@@ -1,7 +1,6 @@
source alpha/Kconfig
source arm/Kconfig
source avr/Kconfig
source cris/Kconfig
source hppa/Kconfig
source i386/Kconfig
source loongarch/Kconfig
target/cris/Kconfig
-2
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@@ -1,2 +0,0 @@
config CRIS
bool
target/cris/cpu-param.h
-16
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@@ -1,16 +0,0 @@
/*
* CRIS cpu parameters for qemu.
*
* Copyright (c) 2007 AXIS Communications AB
* SPDX-License-Identifier: LGPL-2.0+
*/
#ifndef CRIS_CPU_PARAM_H
#define CRIS_CPU_PARAM_H
#define TARGET_LONG_BITS 32
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
target/cris/cpu-qom.h
-32
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@@ -1,32 +0,0 @@
/*
* QEMU CRIS CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#ifndef QEMU_CRIS_CPU_QOM_H
#define QEMU_CRIS_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_CRIS_CPU "cris-cpu"
OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
#endif
target/cris/cpu.c
-323
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@@ -1,323 +0,0 @@
/*
* QEMU CRIS CPU
*
* Copyright (c) 2008 AXIS Communications AB
* Written by Edgar E. Iglesias.
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
#include "mmu.h"
static void cris_cpu_set_pc(CPUState *cs, vaddr value)
{
CRISCPU *cpu = CRIS_CPU(cs);
cpu->env.pc = value;
}
static vaddr cris_cpu_get_pc(CPUState *cs)
{
CRISCPU *cpu = CRIS_CPU(cs);
return cpu->env.pc;
}
static void cris_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
CRISCPU *cpu = CRIS_CPU(cs);
cpu->env.pc = data[0];
}
static bool cris_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
static int cris_cpu_mmu_index(CPUState *cs, bool ifetch)
{
return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG);
}
static void cris_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
CPUCRISState *env = cpu_env(cs);
uint32_t vr;
if (ccc->parent_phases.hold) {
ccc->parent_phases.hold(obj, type);
}
vr = env->pregs[PR_VR];
memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
env->pregs[PR_VR] = vr;
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
#else
cris_mmu_init(env);
env->pregs[PR_CCS] = 0;
#endif
}
static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
char *typename;
#if defined(CONFIG_USER_ONLY)
if (strcasecmp(cpu_model, "any") == 0) {
return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
}
#endif
typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
return oc;
}
static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
cpu_reset(cs);
qemu_init_vcpu(cs);
ccc->parent_realize(dev, errp);
}
#ifndef CONFIG_USER_ONLY
static void cris_cpu_set_irq(void *opaque, int irq, int level)
{
CRISCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
if (irq == CRIS_CPU_IRQ) {
/*
* The PIC passes us the vector for the IRQ as the value it sends
* over the qemu_irq line
*/
cpu->env.interrupt_vector = level;
}
if (level) {
cpu_interrupt(cs, type);
} else {
cpu_reset_interrupt(cs, type);
}
}
#endif
static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
{
if (cpu_env(cpu)->pregs[PR_VR] != 32) {
info->mach = bfd_mach_cris_v0_v10;
info->print_insn = print_insn_crisv10;
} else {
info->mach = bfd_mach_cris_v32;
info->print_insn = print_insn_crisv32;
}
}
static void cris_cpu_initfn(Object *obj)
{
CRISCPU *cpu = CRIS_CPU(obj);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
CPUCRISState *env = &cpu->env;
env->pregs[PR_VR] = ccc->vr;
#ifndef CONFIG_USER_ONLY
/* IRQ and NMI lines. */
qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
#endif
}
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps cris_sysemu_ops = {
.get_phys_page_debug = cris_cpu_get_phys_page_debug,
};
#endif
#include "hw/core/tcg-cpu-ops.h"
static const TCGCPUOps crisv10_tcg_ops = {
.initialize = cris_initialize_crisv10_tcg,
.restore_state_to_opc = cris_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = cris_cpu_tlb_fill,
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
.cpu_exec_halt = cris_cpu_has_work,
.do_interrupt = crisv10_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
static const TCGCPUOps crisv32_tcg_ops = {
.initialize = cris_initialize_tcg,
.restore_state_to_opc = cris_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY
.tlb_fill = cris_cpu_tlb_fill,
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
.cpu_exec_halt = cris_cpu_has_work,
.do_interrupt = cris_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 8;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 10;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 11;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 17;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 32;
cc->tcg_ops = &crisv32_tcg_ops;
}
static void cris_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, cris_cpu_realizefn,
&ccc->parent_realize);
resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL,
&ccc->parent_phases);
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
cc->mmu_index = cris_cpu_mmu_index;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
cc->get_pc = cris_cpu_get_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
dc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
}
#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
{ \
.parent = TYPE_CRIS_CPU, \
.class_init = initfn, \
.name = CRIS_CPU_TYPE_NAME(cpu_model), \
}
static const TypeInfo cris_cpu_model_type_infos[] = {
{
.name = TYPE_CRIS_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(CRISCPU),
.instance_align = __alignof(CRISCPU),
.instance_init = cris_cpu_initfn,
.abstract = true,
.class_size = sizeof(CRISCPUClass),
.class_init = cris_cpu_class_init,
},
DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init),
DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init),
DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init),
DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init),
DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init),
DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init),
};
DEFINE_TYPES(cris_cpu_model_type_infos)
target/cris/cpu.h
-286
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@@ -1,286 +0,0 @@
/*
* CRIS virtual CPU header
*
* Copyright (c) 2007 AXIS Communications AB
* Written by Edgar E. Iglesias
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CRIS_CPU_H
#define CRIS_CPU_H
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#define EXCP_NMI 1
#define EXCP_GURU 2
#define EXCP_BUSFAULT 3
#define EXCP_IRQ 4
#define EXCP_BREAK 5
/* CRIS-specific interrupt pending bits. */
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
/* CRUS CPU device objects interrupt lines. */
/* PIC passes the vector for the IRQ as the value of it sends over qemu_irq */
#define CRIS_CPU_IRQ 0
#define CRIS_CPU_NMI 1
/* Register aliases. R0 - R15 */
#define R_FP 8
#define R_SP 14
#define R_ACR 15
/* Support regs, P0 - P15 */
#define PR_BZ 0
#define PR_VR 1
#define PR_PID 2
#define PR_SRS 3
#define PR_WZ 4
#define PR_EXS 5
#define PR_EDA 6
#define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
#define PR_MOF 7
#define PR_DZ 8
#define PR_EBP 9
#define PR_ERP 10
#define PR_SRP 11
#define PR_NRP 12
#define PR_CCS 13
#define PR_USP 14
#define PRV10_BRP 14
#define PR_SPC 15
/* CPU flags. */
#define Q_FLAG 0x80000000
#define M_FLAG_V32 0x40000000
#define PFIX_FLAG 0x800 /* CRISv10 Only. */
#define F_FLAG_V10 0x400
#define P_FLAG_V10 0x200
#define S_FLAG 0x200
#define R_FLAG 0x100
#define P_FLAG 0x80
#define M_FLAG_V10 0x80
#define U_FLAG 0x40
#define I_FLAG 0x20
#define X_FLAG 0x10
#define N_FLAG 0x08
#define Z_FLAG 0x04
#define V_FLAG 0x02
#define C_FLAG 0x01
#define ALU_FLAGS 0x1F
/* Condition codes. */
#define CC_CC 0
#define CC_CS 1
#define CC_NE 2
#define CC_EQ 3
#define CC_VC 4
#define CC_VS 5
#define CC_PL 6
#define CC_MI 7
#define CC_LS 8
#define CC_HI 9
#define CC_GE 10
#define CC_LT 11
#define CC_GT 12
#define CC_LE 13
#define CC_A 14
#define CC_P 15
typedef struct {
uint32_t hi;
uint32_t lo;
} TLBSet;
typedef struct CPUArchState {
uint32_t regs[16];
/* P0 - P15 are referred to as special registers in the docs. */
uint32_t pregs[16];
/* Pseudo register for the PC. Not directly accessible on CRIS. */
uint32_t pc;
/* Pseudo register for the kernel stack. */
uint32_t ksp;
/* Branch. */
int dslot;
int btaken;
uint32_t btarget;
/* Condition flag tracking. */
uint32_t cc_op;
uint32_t cc_mask;
uint32_t cc_dest;
uint32_t cc_src;
uint32_t cc_result;
/* size of the operation, 1 = byte, 2 = word, 4 = dword. */
int cc_size;
/* X flag at the time of cc snapshot. */
int cc_x;
/* CRIS has certain insns that lockout interrupts. */
int locked_irq;
int interrupt_vector;
int fault_vector;
int trap_vector;
/* FIXME: add a check in the translator to avoid writing to support
register sets beyond the 4th. The ISA allows up to 256! but in
practice there is no core that implements more than 4.
Support function registers are used to control units close to the
core. Accesses do not pass down the normal hierarchy.
*/
uint32_t sregs[4][16];
/* Linear feedback shift reg in the mmu. Used to provide pseudo
randomness for the 'hint' the mmu gives to sw for choosing valid
sets on TLB refills. */
uint32_t mmu_rand_lfsr;
/*
* We just store the stores to the tlbset here for later evaluation
* when the hw needs access to them.
*
* One for I and another for D.
*/
TLBSet tlbsets[2][4][16];
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
/* Members from load_info on are preserved across resets. */
void *load_info;
} CPUCRISState;
/**
* CRISCPU:
* @env: #CPUCRISState
*
* A CRIS CPU.
*/
struct ArchCPU {
CPUState parent_obj;
CPUCRISState env;
};
/**
* CRISCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @vr: Version Register value.
*
* A CRIS CPU model.
*/
struct CRISCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t vr;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_cris_cpu;
void cris_cpu_do_interrupt(CPUState *cpu);
void crisv10_cpu_do_interrupt(CPUState *cpu);
bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void cris_initialize_tcg(void);
void cris_initialize_crisv10_tcg(void);
/* Instead of computing the condition codes after each CRIS instruction,
* QEMU just stores one operand (called CC_SRC), the result
* (called CC_DEST) and the type of operation (called CC_OP). When the
* condition codes are needed, the condition codes can be calculated
* using this information. Condition codes are not generated if they
* are only needed for conditional branches.
*/
enum {
CC_OP_DYNAMIC, /* Use env->cc_op */
CC_OP_FLAGS,
CC_OP_CMP,
CC_OP_MOVE,
CC_OP_ADD,
CC_OP_ADDC,
CC_OP_MCP,
CC_OP_ADDU,
CC_OP_SUB,
CC_OP_SUBU,
CC_OP_NEG,
CC_OP_BTST,
CC_OP_MULS,
CC_OP_MULU,
CC_OP_DSTEP,
CC_OP_MSTEP,
CC_OP_BOUND,
CC_OP_OR,
CC_OP_AND,
CC_OP_XOR,
CC_OP_LSL,
CC_OP_LSR,
CC_OP_ASR,
CC_OP_LZ
};
/* CRIS uses 8k pages. */
#define MMAP_SHIFT TARGET_PAGE_BITS
#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
/* MMU modes definitions */
#define MMU_USER_IDX 1
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0
#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
*pc = env->pc;
*cs_base = 0;
*flags = env->dslot |
(env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
| X_FLAG | PFIX_FLAG));
}
#endif
target/cris/crisv10-decode.h
-112
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@@ -1,112 +0,0 @@
/*
* CRISv10 insn decoding macros.
*
* Copyright (c) 2010 AXIS Communications AB
* Written by Edgar E. Iglesias.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef TARGET_CRIS_CRISV10_DECODE_H
#define TARGET_CRIS_CRISV10_DECODE_H
#define CRISV10_MODE_QIMMEDIATE 0
#define CRISV10_MODE_REG 1
#define CRISV10_MODE_INDIRECT 2
#define CRISV10_MODE_AUTOINC 3
/* Quick Immediate. */
#define CRISV10_QIMM_BCC_R0 0
#define CRISV10_QIMM_BCC_R1 1
#define CRISV10_QIMM_BCC_R2 2
#define CRISV10_QIMM_BCC_R3 3
#define CRISV10_QIMM_BDAP_R0 4
#define CRISV10_QIMM_BDAP_R1 5
#define CRISV10_QIMM_BDAP_R2 6
#define CRISV10_QIMM_BDAP_R3 7
#define CRISV10_QIMM_ADDQ 8
#define CRISV10_QIMM_MOVEQ 9
#define CRISV10_QIMM_SUBQ 10
#define CRISV10_QIMM_CMPQ 11
#define CRISV10_QIMM_ANDQ 12
#define CRISV10_QIMM_ORQ 13
#define CRISV10_QIMM_ASHQ 14
#define CRISV10_QIMM_LSHQ 15
#define CRISV10_REG_ADDX 0
#define CRISV10_REG_MOVX 1
#define CRISV10_REG_SUBX 2
#define CRISV10_REG_LSL 3
#define CRISV10_REG_ADDI 4
#define CRISV10_REG_BIAP 5
#define CRISV10_REG_NEG 6
#define CRISV10_REG_BOUND 7
#define CRISV10_REG_ADD 8
#define CRISV10_REG_MOVE_R 9
#define CRISV10_REG_MOVE_SPR_R 9
#define CRISV10_REG_MOVE_R_SPR 8
#define CRISV10_REG_SUB 10
#define CRISV10_REG_CMP 11
#define CRISV10_REG_AND 12
#define CRISV10_REG_OR 13
#define CRISV10_REG_ASR 14
#define CRISV10_REG_LSR 15
#define CRISV10_REG_BTST 3
#define CRISV10_REG_SCC 4
#define CRISV10_REG_SETF 6
#define CRISV10_REG_CLEARF 7
#define CRISV10_REG_BIAP 5
#define CRISV10_REG_ABS 10
#define CRISV10_REG_DSTEP 11
#define CRISV10_REG_LZ 12
#define CRISV10_REG_NOT 13
#define CRISV10_REG_SWAP 13
#define CRISV10_REG_XOR 14
#define CRISV10_REG_MSTEP 15
/* Indirect, var size. */
#define CRISV10_IND_TEST 14
#define CRISV10_IND_MUL 4
#define CRISV10_IND_BDAP_M 5
#define CRISV10_IND_ADD 8
#define CRISV10_IND_MOVE_M_R 9
/* indirect fixed size. */
#define CRISV10_IND_ADDX 0
#define CRISV10_IND_MOVX 1
#define CRISV10_IND_SUBX 2
#define CRISV10_IND_CMPX 3
#define CRISV10_IND_JUMP_M 4
#define CRISV10_IND_DIP 5
#define CRISV10_IND_JUMP_R 6
#define CRISV17_IND_ADDC 6
#define CRISV10_IND_BOUND 7
#define CRISV10_IND_BCC_M 7
#define CRISV10_IND_MOVE_M_SPR 8
#define CRISV10_IND_MOVE_SPR_M 9
#define CRISV10_IND_SUB 10
#define CRISV10_IND_CMP 11
#define CRISV10_IND_AND 12
#define CRISV10_IND_OR 13
#define CRISV10_IND_MOVE_R_M 15
#define CRISV10_IND_MOVEM_M_R 14
#define CRISV10_IND_MOVEM_R_M 15
#endif
target/cris/crisv32-decode.h
-133
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@@ -1,133 +0,0 @@
/*
* CRIS insn decoding macros.
*
* Copyright (c) 2007 AXIS Communications AB
* Written by Edgar E. Iglesias.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CRISV32_DECODE_H
#define CRISV32_DECODE_H
/* Convenient binary macros. */
#define HEX__(n) 0x##n##LU
#define B8__(x) ((x&0x0000000FLU)?1:0) \
+ ((x&0x000000F0LU)?2:0) \
+ ((x&0x00000F00LU)?4:0) \
+ ((x&0x0000F000LU)?8:0) \
+ ((x&0x000F0000LU)?16:0) \
+ ((x&0x00F00000LU)?32:0) \
+ ((x&0x0F000000LU)?64:0) \
+ ((x&0xF0000000LU)?128:0)
#define B8(d) ((unsigned char)B8__(HEX__(d)))
/* Quick imm. */
#define DEC_BCCQ {B8(00000000), B8(11110000)}
#define DEC_ADDOQ {B8(00010000), B8(11110000)}
#define DEC_ADDQ {B8(00100000), B8(11111100)}
#define DEC_MOVEQ {B8(00100100), B8(11111100)}
#define DEC_SUBQ {B8(00101000), B8(11111100)}
#define DEC_CMPQ {B8(00101100), B8(11111100)}
#define DEC_ANDQ {B8(00110000), B8(11111100)}
#define DEC_ORQ {B8(00110100), B8(11111100)}
#define DEC_BTSTQ {B8(00111000), B8(11111110)}
#define DEC_ASRQ {B8(00111010), B8(11111110)}
#define DEC_LSLQ {B8(00111100), B8(11111110)}
#define DEC_LSRQ {B8(00111110), B8(11111110)}
/* Register. */
#define DEC_MOVU_R {B8(01000100), B8(11111110)}
#define DEC_MOVU_R {B8(01000100), B8(11111110)}
#define DEC_MOVS_R {B8(01000110), B8(11111110)}
#define DEC_MOVE_R {B8(01100100), B8(11111100)}
#define DEC_MOVE_RP {B8(01100011), B8(11111111)}
#define DEC_MOVE_PR {B8(01100111), B8(11111111)}
#define DEC_DSTEP_R {B8(01101111), B8(11111111)}
#define DEC_MOVE_RS {B8(10110111), B8(11111111)}
#define DEC_MOVE_SR {B8(11110111), B8(11111111)}
#define DEC_ADDU_R {B8(01000000), B8(11111110)}
#define DEC_ADDS_R {B8(01000010), B8(11111110)}
#define DEC_ADD_R {B8(01100000), B8(11111100)}
#define DEC_ADDI_R {B8(01010000), B8(11111100)}
#define DEC_MULS_R {B8(11010000), B8(11111100)}
#define DEC_MULU_R {B8(10010000), B8(11111100)}
#define DEC_ADDI_ACR {B8(01010100), B8(11111100)}
#define DEC_NEG_R {B8(01011000), B8(11111100)}
#define DEC_BOUND_R {B8(01011100), B8(11111100)}
#define DEC_SUBU_R {B8(01001000), B8(11111110)}
#define DEC_SUBS_R {B8(01001010), B8(11111110)}
#define DEC_SUB_R {B8(01101000), B8(11111100)}
#define DEC_CMP_R {B8(01101100), B8(11111100)}
#define DEC_AND_R {B8(01110000), B8(11111100)}
#define DEC_ABS_R {B8(01101011), B8(11111111)}
#define DEC_LZ_R {B8(01110011), B8(11111111)}
#define DEC_MCP_R {B8(01111111), B8(11111111)}
#define DEC_SWAP_R {B8(01110111), B8(11111111)}
#define DEC_XOR_R {B8(01111011), B8(11111111)}
#define DEC_LSL_R {B8(01001100), B8(11111100)}
#define DEC_LSR_R {B8(01111100), B8(11111100)}
#define DEC_ASR_R {B8(01111000), B8(11111100)}
#define DEC_OR_R {B8(01110100), B8(11111100)}
#define DEC_BTST_R {B8(01001111), B8(11111111)}
/* Fixed. */
#define DEC_SETF {B8(01011011), B8(11111111)}
#define DEC_CLEARF {B8(01011111), B8(11111111)}
/* Memory. */
#define DEC_ADDU_M {B8(10000000), B8(10111110)}
#define DEC_ADDS_M {B8(10000010), B8(10111110)}
#define DEC_MOVU_M {B8(10000100), B8(10111110)}
#define DEC_MOVS_M {B8(10000110), B8(10111110)}
#define DEC_SUBU_M {B8(10001000), B8(10111110)}
#define DEC_SUBS_M {B8(10001010), B8(10111110)}
#define DEC_CMPU_M {B8(10001100), B8(10111110)}
#define DEC_CMPS_M {B8(10001110), B8(10111110)}
#define DEC_ADDO_M {B8(10010100), B8(10111100)}
#define DEC_BOUND_M {B8(10011100), B8(10111100)}
#define DEC_ADD_M {B8(10100000), B8(10111100)}
#define DEC_MOVE_MR {B8(10100100), B8(10111100)}
#define DEC_SUB_M {B8(10101000), B8(10111100)}
#define DEC_CMP_M {B8(10101100), B8(10111100)}
#define DEC_AND_M {B8(10110000), B8(10111100)}
#define DEC_OR_M {B8(10110100), B8(10111100)}
#define DEC_TEST_M {B8(10111000), B8(10111100)}
#define DEC_MOVE_RM {B8(10111100), B8(10111100)}
#define DEC_ADDC_R {B8(01010111), B8(11111111)}
#define DEC_ADDC_MR {B8(10011010), B8(10111111)}
#define DEC_LAPCQ {B8(10010111), B8(11111111)}
#define DEC_LAPC_IM {B8(11010111), B8(11111111)}
#define DEC_MOVE_MP {B8(10100011), B8(10111111)}
#define DEC_MOVE_PM {B8(10100111), B8(10111111)}
#define DEC_SCC_R {B8(01010011), B8(11111111)}
#define DEC_RFE_ETC {B8(10010011), B8(11111111)}
#define DEC_JUMP_P {B8(10011111), B8(11111111)}
#define DEC_BCC_IM {B8(11011111), B8(11111111)}
#define DEC_JAS_R {B8(10011011), B8(11111111)}
#define DEC_JASC_R {B8(10110011), B8(11111111)}
#define DEC_JAS_IM {B8(11011011), B8(11111111)}
#define DEC_JASC_IM {B8(11110011), B8(11111111)}
#define DEC_BAS_IM {B8(11101011), B8(11111111)}
#define DEC_BASC_IM {B8(11101111), B8(11111111)}
#define DEC_MOVEM_MR {B8(10111011), B8(10111111)}
#define DEC_MOVEM_RM {B8(10111111), B8(10111111)}
#define DEC_FTAG_FIDX_D_M {B8(10101011), B8(11111111)}
#define DEC_FTAG_FIDX_I_M {B8(11010011), B8(11111111)}
#endif
target/cris/gdbstub.c
-127
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@@ -1,127 +0,0 @@
/*
* CRIS gdb server stub
*
* Copyright (c) 2003-2005 Fabrice Bellard
* Copyright (c) 2013 SUSE LINUX Products GmbH
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "gdbstub/helpers.h"
int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
CPUCRISState *env = cpu_env(cs);
if (n < 15) {
return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n == 15) {
return gdb_get_reg32(mem_buf, env->pc);
}
if (n < 32) {
switch (n) {
case 16:
return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
case 17:
return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
case 20:
case 21:
return gdb_get_reg16(mem_buf, env->pregs[n - 16]);
default:
if (n >= 23) {
return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
}
break;
}
}
return 0;
}
int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
CPUCRISState *env = cpu_env(cs);
uint8_t srs;
srs = env->pregs[PR_SRS];
if (n < 16) {
return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n >= 21 && n < 32) {
return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
}
if (n >= 33 && n < 49) {
return gdb_get_reg32(mem_buf, env->sregs[srs][n - 33]);
}
switch (n) {
case 16:
return gdb_get_reg8(mem_buf, env->pregs[0]);
case 17:
return gdb_get_reg8(mem_buf, env->pregs[1]);
case 18:
return gdb_get_reg32(mem_buf, env->pregs[2]);
case 19:
return gdb_get_reg8(mem_buf, srs);
case 20:
return gdb_get_reg16(mem_buf, env->pregs[4]);
case 32:
return gdb_get_reg32(mem_buf, env->pc);
}
return 0;
}
int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPUCRISState *env = cpu_env(cs);
uint32_t tmp;
if (n > 49) {
return 0;
}
tmp = ldl_p(mem_buf);
if (n < 16) {
env->regs[n] = tmp;
}
if (n >= 21 && n < 32) {
env->pregs[n - 16] = tmp;
}
/* FIXME: Should support function regs be writable? */
switch (n) {
case 16:
return 1;
case 17:
return 1;
case 18:
env->pregs[PR_PID] = tmp;
break;
case 19:
return 1;
case 20:
return 2;
case 32:
env->pc = tmp;
break;
}
return 4;
}
target/cris/helper.c
-287
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@@ -1,287 +0,0 @@
/*
* CRIS helper routines.
*
* Copyright (c) 2007 AXIS Communications AB
* Written by Edgar E. Iglesias.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "mmu.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
//#define CRIS_HELPER_DEBUG
#ifdef CRIS_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif
static void cris_shift_ccs(CPUCRISState *env)
{
uint32_t ccs;
/* Apply the ccs shift. */
ccs = env->pregs[PR_CCS];
ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
env->pregs[PR_CCS] = ccs;
}
bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
CPUCRISState *env = cpu_env(cs);
struct cris_mmu_result res;
int prot, miss;
target_ulong phy;
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
access_type, mmu_idx, 0);
if (likely(!miss)) {
/*
* Mask off the cache selection bit. The ETRAX busses do not
* see the top bit.
*/
phy = res.phy & ~0x80000000;
prot = res.prot;
tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
prot, mmu_idx, TARGET_PAGE_SIZE);
return true;
}
if (probe) {
return false;
}
if (cs->exception_index == EXCP_BUSFAULT) {
cpu_abort(cs, "CRIS: Illegal recursive bus fault."
"addr=%" VADDR_PRIx " access_type=%d\n",
address, access_type);
}
env->pregs[PR_EDA] = address;
cs->exception_index = EXCP_BUSFAULT;
env->fault_vector = res.bf_vec;
if (retaddr) {
if (cpu_restore_state(cs, retaddr)) {
/* Evaluate flags after retranslation. */
helper_top_evaluate_flags(env);
}
}
cpu_loop_exit(cs);
}
void crisv10_cpu_do_interrupt(CPUState *cs)
{
CPUCRISState *env = cpu_env(cs);
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
cs->exception_index,
cs->interrupt_request);
if (env->dslot) {
/* CRISv10 never takes interrupts while in a delay-slot. */
cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
}
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PRV10_BRP] = env->pc;
break;
case EXCP_NMI:
/* NMI is hardwired to vector zero. */
ex_vec = 0;
env->pregs[PR_CCS] &= ~M_FLAG_V10;
env->pregs[PRV10_BRP] = env->pc;
break;
case EXCP_BUSFAULT:
cpu_abort(cs, "Unhandled busfault");
break;
default:
/* The interrupt controller gives us the vector. */
ex_vec = env->interrupt_vector;
/* Normal interrupts are taken between
TB's. env->pc is valid here. */
env->pregs[PR_ERP] = env->pc;
break;
}
if (env->pregs[PR_CCS] & U_FLAG) {
/* Swap stack pointers. */
env->pregs[PR_USP] = env->regs[R_SP];
env->regs[R_SP] = env->ksp;
}
/* Now that we are in kernel mode, load the handlers address. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
env->locked_irq = 1;
env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec,
env->pregs[PR_CCS],
env->pregs[PR_PID],
env->pregs[PR_ERP]);
}
void cris_cpu_do_interrupt(CPUState *cs)
{
CPUCRISState *env = cpu_env(cs);
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
cs->exception_index,
cs->interrupt_request);
switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PR_ERP] = env->pc;
break;
case EXCP_NMI:
/* NMI is hardwired to vector zero. */
ex_vec = 0;
env->pregs[PR_CCS] &= ~M_FLAG_V32;
env->pregs[PR_NRP] = env->pc;
break;
case EXCP_BUSFAULT:
ex_vec = env->fault_vector;
env->pregs[PR_ERP] = env->pc;
break;
default:
/* The interrupt controller gives us the vector. */
ex_vec = env->interrupt_vector;
/* Normal interrupts are taken between
TB's. env->pc is valid here. */
env->pregs[PR_ERP] = env->pc;
break;
}
/* Fill in the IDX field. */
env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
if (env->dslot) {
D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
" ERP=%x pid=%x ccs=%x cc=%d %x\n",
ex_vec, env->pc, env->dslot,
env->regs[R_SP],
env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS],
env->cc_op, env->cc_mask);
/* We loose the btarget, btaken state here so rexec the
branch. */
env->pregs[PR_ERP] -= env->dslot;
/* Exception starts with dslot cleared. */
env->dslot = 0;
}
if (env->pregs[PR_CCS] & U_FLAG) {
/* Swap stack pointers. */
env->pregs[PR_USP] = env->regs[R_SP];
env->regs[R_SP] = env->ksp;
}
/* Apply the CRIS CCS shift. Clears U if set. */
cris_shift_ccs(env);
/* Now that we are in kernel mode, load the handlers address.
This load may not fault, real hw leaves that behaviour as
undefined. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
/* Clear the excption_index to avoid spurious hw_aborts for recursive
bus faults. */
cs->exception_index = -1;
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec,
env->pregs[PR_CCS],
env->pregs[PR_PID],
env->pregs[PR_ERP]);
}
hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
CRISCPU *cpu = CRIS_CPU(cs);
uint32_t phy = addr;
struct cris_mmu_result res;
int miss;
miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_DATA_LOAD, 0, 1);
/* If D TLB misses, try I TLB. */
if (miss) {
miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1);
}
if (!miss) {
phy = res.phy;
}
D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
return phy;
}
bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
CPUCRISState *env = cpu_env(cs);
bool ret = false;
if (interrupt_request & CPU_INTERRUPT_HARD
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
cs->exception_index = EXCP_IRQ;
cc->tcg_ops->do_interrupt(cs);
ret = true;
}
if (interrupt_request & CPU_INTERRUPT_NMI) {
unsigned int m_flag_archval;
if (env->pregs[PR_VR] < 32) {
m_flag_archval = M_FLAG_V10;
} else {
m_flag_archval = M_FLAG_V32;
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
cs->exception_index = EXCP_NMI;
cc->tcg_ops->do_interrupt(cs);
ret = true;
}
}
return ret;
}
target/cris/helper.h
-23
View File
@@ -1,23 +0,0 @@
DEF_HELPER_2(raise_exception, noreturn, env, i32)
DEF_HELPER_2(tlb_flush_pid, void, env, i32)
DEF_HELPER_2(spc_write, void, env, i32)
DEF_HELPER_1(rfe, void, env)
DEF_HELPER_1(rfn, void, env)
DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
DEF_HELPER_FLAGS_4(btst, TCG_CALL_NO_SE, i32, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_NO_SE, i32, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_NO_SE, i32, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_NO_SE, i32, env,
i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_NO_SE, i32, env,
i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_NO_SE, i32, env,
i32, i32, i32, i32)
DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_NO_SE, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_NO_SE, i32, env, i32, i32)
DEF_HELPER_1(evaluate_flags, void, env)
DEF_HELPER_1(top_evaluate_flags, void, env)
target/cris/machine.c
-93
View File
@@ -1,93 +0,0 @@
/*
* CRIS virtual CPU state save/load support
*
* Copyright (c) 2012 Red Hat, Inc.
* Written by Juan Quintela <quintela@redhat.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/cpu.h"
static const VMStateDescription vmstate_tlbset = {
.name = "cpu/tlbset",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(lo, TLBSet),
VMSTATE_UINT32(hi, TLBSet),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_cris_env = {
.name = "env",
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, CPUCRISState, 16),
VMSTATE_UINT32_ARRAY(pregs, CPUCRISState, 16),
VMSTATE_UINT32(pc, CPUCRISState),
VMSTATE_UINT32(ksp, CPUCRISState),
VMSTATE_INT32(dslot, CPUCRISState),
VMSTATE_INT32(btaken, CPUCRISState),
VMSTATE_UINT32(btarget, CPUCRISState),
VMSTATE_UINT32(cc_op, CPUCRISState),
VMSTATE_UINT32(cc_mask, CPUCRISState),
VMSTATE_UINT32(cc_dest, CPUCRISState),
VMSTATE_UINT32(cc_src, CPUCRISState),
VMSTATE_UINT32(cc_result, CPUCRISState),
VMSTATE_INT32(cc_size, CPUCRISState),
VMSTATE_INT32(cc_x, CPUCRISState),
VMSTATE_INT32(locked_irq, CPUCRISState),
VMSTATE_INT32(interrupt_vector, CPUCRISState),
VMSTATE_INT32(fault_vector, CPUCRISState),
VMSTATE_INT32(trap_vector, CPUCRISState),
VMSTATE_UINT32_ARRAY(sregs[0], CPUCRISState, 16),
VMSTATE_UINT32_ARRAY(sregs[1], CPUCRISState, 16),
VMSTATE_UINT32_ARRAY(sregs[2], CPUCRISState, 16),
VMSTATE_UINT32_ARRAY(sregs[3], CPUCRISState, 16),
VMSTATE_UINT32(mmu_rand_lfsr, CPUCRISState),
VMSTATE_STRUCT_ARRAY(tlbsets[0][0], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_STRUCT_ARRAY(tlbsets[0][1], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_STRUCT_ARRAY(tlbsets[0][2], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_STRUCT_ARRAY(tlbsets[0][3], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_STRUCT_ARRAY(tlbsets[1][0], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_STRUCT_ARRAY(tlbsets[1][1], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_STRUCT_ARRAY(tlbsets[1][2], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_STRUCT_ARRAY(tlbsets[1][3], CPUCRISState, 16, 0,
vmstate_tlbset, TLBSet),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_cris_cpu = {
.name = "cpu",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_CPU(),
VMSTATE_STRUCT(env, CRISCPU, 1, vmstate_cris_env, CPUCRISState),
VMSTATE_END_OF_LIST()
}
};
target/cris/meson.build
-17
View File
@@ -1,17 +0,0 @@
cris_ss = ss.source_set()
cris_ss.add(files(
'cpu.c',
'gdbstub.c',
'op_helper.c',
'translate.c',
))
cris_system_ss = ss.source_set()
cris_system_ss.add(files(
'helper.c',
'machine.c',
'mmu.c',
))
target_arch += {'cris': cris_ss}
target_system_arch += {'cris': cris_system_ss}

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