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hw/misc: Add a basic Aspeed LPC controller model

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This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater
2021-03-09 12:01:28 +01:00
parent 6820588efa
commit 2ecf17264d
7 changed files with 192 additions and 2 deletions
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docs/system/arm/aspeed.rst
+1 -1
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@@ -48,6 +48,7 @@ Supported devices
* UART
* Ethernet controllers
* Front LEDs (PCA9552 on I2C bus)
* LPC Peripheral Controller (a subset of subdevices are supported)
Missing devices
@@ -56,7 +57,6 @@ Missing devices
* Coprocessor support
* ADC (out of tree implementation)
* PWM and Fan Controller
* LPC Bus Controller
* Slave GPIO Controller
* Super I/O Controller
* Hash/Crypto Engine