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accel/tcg: Add cpu_ld*_code_mmu
At least RISC-V has the need to be able to perform a read using execute permissions, outside of translation. Add helpers to facilitate this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-9-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-9-richard.henderson@linaro.org>
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@@ -445,6 +445,15 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
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# define cpu_stq_mmu cpu_stq_le_mmu
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#endif
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uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
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