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target/alpha: Fix user-only floating-point exceptions

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Record the software fp control register, as set by the
osf_setsysinfo syscall.  Add those masked exceptions
to fpcr_exc_enable.  Do not raise a signal for masked
fp exceptions.

Fixes: https://bugs.launchpad.net/bugs/1701835
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2019-05-19 07:30:03 -07:00
parent 4a24793290
commit 21ba856499
5 changed files with 130 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/alpha/cpu.h
+42
View File
@@ -198,6 +198,8 @@ enum {
#define SWCR_STATUS_DNO (1U << 22)
#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
#define SWCR_STATUS_TO_EXCSUM_SHIFT 16
#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
/* MMU modes definitions */
@@ -235,6 +237,9 @@ struct CPUAlphaState {
/* The FPCR, and disassembled portions thereof. */
uint32_t fpcr;
#ifdef CONFIG_USER_ONLY
uint32_t swcr;
#endif
uint32_t fpcr_exc_enable;
float_status fp_status;
uint8_t fpcr_dyn_round;
@@ -501,4 +506,41 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
*pflags = env->flags & ENV_FLAG_TB_MASK;
}
#ifdef CONFIG_USER_ONLY
/* Copied from linux ieee_swcr_to_fpcr. */
static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
{
uint64_t fpcr = 0;
fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
| SWCR_TRAP_ENABLE_DZE
| SWCR_TRAP_ENABLE_OVF)) << 48;
fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
| SWCR_TRAP_ENABLE_INE)) << 57;
fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
return fpcr;
}
/* Copied from linux ieee_fpcr_to_swcr. */
static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
{
uint64_t swcr = 0;
swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
| SWCR_TRAP_ENABLE_DZE
| SWCR_TRAP_ENABLE_OVF);
swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
return swcr;
}
#endif /* CONFIG_USER_ONLY */
#endif /* ALPHA_CPU_H */
target/alpha/fpu_helper.c
+18 -3
View File
@@ -91,10 +91,25 @@ void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
if (exc) {
env->fpcr |= exc;
exc &= ~ignore;
if (exc) {
exc &= env->fpcr_exc_enable;
fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
#ifdef CONFIG_USER_ONLY
/*
* In user mode, the kernel's software handler only
* delivers a signal if the exception is enabled.
*/
if (!(exc & env->fpcr_exc_enable)) {
return;
}
#else
/*
* In system mode, the software handler gets invoked
* for any non-ignored exception.
*/
if (!exc) {
return;
}
#endif
exc &= env->fpcr_exc_enable;
fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
}
}
target/alpha/helper.c
+18 -2
View File
@@ -29,12 +29,12 @@
#define CONVERT_BIT(X, SRC, DST) \
(SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
uint64_t cpu_alpha_load_fpcr(CPUAlphaState *env)
{
return (uint64_t)env->fpcr << 32;
}
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val)
{
uint32_t fpcr = val >> 32;
uint32_t t = 0;
@@ -67,6 +67,22 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ);
env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0;
#ifdef CONFIG_USER_ONLY
/*
* Override some of these bits with the contents of ENV->SWCR.
* In system mode, some of these would trap to the kernel, at
* which point the kernel's handler would emulate and apply
* the software exception mask.
*/
if (env->swcr & SWCR_MAP_DMZ) {
env->fp_status.flush_inputs_to_zero = 1;
}
if (env->swcr & SWCR_MAP_UMZ) {
env->fp_status.flush_to_zero = 1;
}
env->fpcr_exc_enable &= ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32);
#endif
}
uint64_t helper_load_fpcr(CPUAlphaState *env)