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meson: rename included C source files to .c.inc

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With Makefiles that have automatically generated dependencies, you
generated includes are set as dependencies of the Makefile, so that they
are built before everything else and they are available when first
building the .c files.

Alternatively you can use a fine-grained dependency, e.g.

        target/arm/translate.o: target/arm/decode-neon-shared.inc.c

With Meson you have only one choice and it is a third option, namely
"build at the beginning of the corresponding target"; the way you
express it is to list the includes in the sources of that target.

The problem is that Meson decides if something is a source vs. a
generated include by looking at the extension: '.c', '.cc', '.m', '.C'
are sources, while everything else is considered an include---including
'.inc.c'.

Use '.c.inc' to avoid this, as it is consistent with our other convention
of using '.rst.inc' for included reStructuredText files.  The editorconfig
file is adjusted.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
2020-08-21 06:18:30 -04:00
parent 243af0225a
commit 139c1837db
99 changed files with 175 additions and 174 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.editorconfig
+2 -1
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@@ -22,9 +22,10 @@ indent_style = tab
indent_size = 8 indent_size = 8
file_type_emacs = makefile file_type_emacs = makefile
[*.{c,h}] [*.{c,h,c.inc,h.inc}]
indent_style = space indent_style = space
indent_size = 4 indent_size = 4
file_type_emacs = c
[*.sh] [*.sh]
indent_style = space indent_style = space
.gitignore
+2 -2
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@@ -18,7 +18,7 @@
/ui/shader/texture-blit-frag.h /ui/shader/texture-blit-frag.h
/ui/shader/texture-blit-vert.h /ui/shader/texture-blit-vert.h
/ui/shader/texture-blit-flip-vert.h /ui/shader/texture-blit-flip-vert.h
/ui/input-keymap-*.c /ui/input-keymap-*.c.inc
*-timestamp *-timestamp
/*-softmmu /*-softmmu
/*-darwin-user /*-darwin-user
@@ -161,4 +161,4 @@ trace-dtrace-root.h
trace-dtrace-root.dtrace trace-dtrace-root.dtrace
trace-ust-all.h trace-ust-all.h
trace-ust-all.c trace-ust-all.c
/target/arm/decode-sve.inc.c /target/arm/decode-sve.c.inc
Makefile
+18 -18
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@@ -289,28 +289,28 @@ KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen
KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv
KEYCODEMAP_FILES = \ KEYCODEMAP_FILES = \
ui/input-keymap-atset1-to-qcode.c \ ui/input-keymap-atset1-to-qcode.c.inc \
ui/input-keymap-linux-to-qcode.c \ ui/input-keymap-linux-to-qcode.c.inc \
ui/input-keymap-qcode-to-atset1.c \ ui/input-keymap-qcode-to-atset1.c.inc \
ui/input-keymap-qcode-to-atset2.c \ ui/input-keymap-qcode-to-atset2.c.inc \
ui/input-keymap-qcode-to-atset3.c \ ui/input-keymap-qcode-to-atset3.c.inc \
ui/input-keymap-qcode-to-linux.c \ ui/input-keymap-qcode-to-linux.c.inc \
ui/input-keymap-qcode-to-qnum.c \ ui/input-keymap-qcode-to-qnum.c.inc \
ui/input-keymap-qcode-to-sun.c \ ui/input-keymap-qcode-to-sun.c.inc \
ui/input-keymap-qnum-to-qcode.c \ ui/input-keymap-qnum-to-qcode.c.inc \
ui/input-keymap-usb-to-qcode.c \ ui/input-keymap-usb-to-qcode.c.inc \
ui/input-keymap-win32-to-qcode.c \ ui/input-keymap-win32-to-qcode.c.inc \
ui/input-keymap-x11-to-qcode.c \ ui/input-keymap-x11-to-qcode.c.inc \
ui/input-keymap-xorgevdev-to-qcode.c \ ui/input-keymap-xorgevdev-to-qcode.c.inc \
ui/input-keymap-xorgkbd-to-qcode.c \ ui/input-keymap-xorgkbd-to-qcode.c.inc \
ui/input-keymap-xorgxquartz-to-qcode.c \ ui/input-keymap-xorgxquartz-to-qcode.c.inc \
ui/input-keymap-xorgxwin-to-qcode.c \ ui/input-keymap-xorgxwin-to-qcode.c.inc \
ui/input-keymap-osx-to-qcode.c \ ui/input-keymap-osx-to-qcode.c.inc \
$(NULL) $(NULL)
generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES) generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES)
ui/input-keymap-%.c: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs ui/input-keymap-%.c.inc: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs
$(call quiet-command,\ $(call quiet-command,\
stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \ stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \
test -e $(KEYCODEMAP_GEN) && \ test -e $(KEYCODEMAP_GEN) && \
accel/tcg/atomic_common.inc.c → accel/tcg/atomic_common.c.inc
View File
accel/tcg/cputlb.c
+1 -1
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@@ -2354,7 +2354,7 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
#define ATOMIC_MMU_CLEANUP #define ATOMIC_MMU_CLEANUP
#define ATOMIC_MMU_IDX get_mmuidx(oi) #define ATOMIC_MMU_IDX get_mmuidx(oi)
#include "atomic_common.inc.c" #include "atomic_common.c.inc"
#define DATA_SIZE 1 #define DATA_SIZE 1
#include "atomic_template.h" #include "atomic_template.h"
accel/tcg/user-exec.c
+1 -1
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@@ -1189,7 +1189,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
#define EXTRA_ARGS #define EXTRA_ARGS
#include "atomic_common.inc.c" #include "atomic_common.c.inc"
#define DATA_SIZE 1 #define DATA_SIZE 1
#include "atomic_template.h" #include "atomic_template.h"
contrib/gitdm/filetypes.txt
+1 -1
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@@ -42,7 +42,7 @@ order build,interface,tests,code,documentation,devel-doc,blobs
# (most common languages first # (most common languages first
# #
filetype code \.c$ # C filetype code \.c$ # C
filetype code \.inc.c$ # C filetype code \.c.inc$ # C
filetype code \.C$ # C++ filetype code \.C$ # C++
filetype code \.cpp$ # C++ filetype code \.cpp$ # C++
filetype code \.c\+\+$ # C++ filetype code \.c\+\+$ # C++
exec.c
+2 -2
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@@ -3659,7 +3659,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
#define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
#define RCU_READ_LOCK(...) rcu_read_lock() #define RCU_READ_LOCK(...) rcu_read_lock()
#define RCU_READ_UNLOCK(...) rcu_read_unlock() #define RCU_READ_UNLOCK(...) rcu_read_unlock()
#include "memory_ldst.inc.c" #include "memory_ldst.c.inc"
int64_t address_space_cache_init(MemoryRegionCache *cache, int64_t address_space_cache_init(MemoryRegionCache *cache,
AddressSpace *as, AddressSpace *as,
@@ -3795,7 +3795,7 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
#define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
#define RCU_READ_LOCK() ((void)0) #define RCU_READ_LOCK() ((void)0)
#define RCU_READ_UNLOCK() ((void)0) #define RCU_READ_UNLOCK() ((void)0)
#include "memory_ldst.inc.c" #include "memory_ldst.c.inc"
/* virtual memory access for debug (includes writing to ROM) */ /* virtual memory access for debug (includes writing to ROM) */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
fpu/softfloat-specialize.inc.c → fpu/softfloat-specialize.c.inc
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fpu/softfloat.c
+1 -1
View File
@@ -621,7 +621,7 @@ static inline float64 float64_pack_raw(FloatParts p)
| are propagated from function inputs to output. These details are target- | are propagated from function inputs to output. These details are target-
| specific. | specific.
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#include "softfloat-specialize.inc.c" #include "softfloat-specialize.c.inc"
/* Canonicalize EXP and FRAC, setting CLS. */ /* Canonicalize EXP and FRAC, setting CLS. */
static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm, static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm,
include/tcg/tcg.h
+1 -1
View File
@@ -636,7 +636,7 @@ struct TCGContext {
/* Track which vCPU triggers events */ /* Track which vCPU triggers events */
CPUState *cpu; /* *_trans */ CPUState *cpu; /* *_trans */
/* These structures are private to tcg-target.inc.c. */ /* These structures are private to tcg-target.c.inc. */
#ifdef TCG_TARGET_NEED_LDST_LABELS #ifdef TCG_TARGET_NEED_LDST_LABELS
QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
#endif #endif
memory_ldst.inc.c → memory_ldst.c.inc
View File
scripts/clean-includes
+1 -1
View File
@@ -113,7 +113,7 @@ EOT
for f in "$@"; do for f in "$@"; do
case "$f" in case "$f" in
*.inc.c) *.c.inc)
# These aren't standalone C source files # These aren't standalone C source files
echo "SKIPPING $f (not a standalone source file)" echo "SKIPPING $f (not a standalone source file)"
continue continue
target/arm/Makefile.objs
+20 -20
View File
@@ -13,66 +13,66 @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) target/arm/decode-sve.c.inc: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE) target/arm/decode-neon-shared.c.inc: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE) target/arm/decode-neon-dp.c.inc: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE) target/arm/decode-neon-ls.c.inc: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE) target/arm/decode-vfp.c.inc: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE) target/arm/decode-vfp-uncond.c.inc: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) target/arm/decode-a32.c.inc: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) target/arm/decode-a32-uncond.c.inc: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) target/arm/decode-t32.c.inc: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) target/arm/decode-t16.c.inc: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate-sve.o: target/arm/decode-sve.c.inc
target/arm/translate.o: target/arm/decode-neon-shared.inc.c target/arm/translate.o: target/arm/decode-neon-shared.c.inc
target/arm/translate.o: target/arm/decode-neon-dp.inc.c target/arm/translate.o: target/arm/decode-neon-dp.c.inc
target/arm/translate.o: target/arm/decode-neon-ls.inc.c target/arm/translate.o: target/arm/decode-neon-ls.c.inc
target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp.c.inc
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.c.inc
target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32.c.inc
target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.c.inc
target/arm/translate.o: target/arm/decode-t32.inc.c target/arm/translate.o: target/arm/decode-t32.c.inc
target/arm/translate.o: target/arm/decode-t16.inc.c target/arm/translate.o: target/arm/decode-t16.c.inc
obj-y += tlb_helper.o debug_helper.o obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o obj-y += translate.o op_helper.o
target/arm/translate-neon.inc.c → target/arm/translate-neon.c.inc
+3 -3
View File
@@ -50,9 +50,9 @@ static inline int rsub_8(DisasContext *s, int x)
} }
/* Include the generated Neon decoder */ /* Include the generated Neon decoder */
#include "decode-neon-dp.inc.c" #include "decode-neon-dp.c.inc"
#include "decode-neon-ls.inc.c" #include "decode-neon-ls.c.inc"
#include "decode-neon-shared.inc.c" #include "decode-neon-shared.c.inc"
/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
* where 0 is the least significant end of the register. * where 0 is the least significant end of the register.
target/arm/translate-sve.c
+1 -1
View File
@@ -100,7 +100,7 @@ static inline int msz_dtype(DisasContext *s, int msz)
* Include the generated decoder. * Include the generated decoder.
*/ */
#include "decode-sve.inc.c" #include "decode-sve.c.inc"
/* /*
* Implement all of the translator functions referenced by the decoder. * Implement all of the translator functions referenced by the decoder.
target/arm/translate-vfp.inc.c → target/arm/translate-vfp.c.inc
+2 -2
View File
@@ -27,8 +27,8 @@
*/ */
/* Include the generated VFP decoder */ /* Include the generated VFP decoder */
#include "decode-vfp.inc.c" #include "decode-vfp.c.inc"
#include "decode-vfp-uncond.inc.c" #include "decode-vfp-uncond.c.inc"
/* /*
* The imm8 encodes the sign bit, enough bits to represent an exponent in * The imm8 encodes the sign bit, enough bits to represent an exponent in
target/arm/translate.c
+6 -6
View File
@@ -1176,8 +1176,8 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
#define ARM_CP_RW_BIT (1 << 20) #define ARM_CP_RW_BIT (1 << 20)
/* Include the VFP and Neon decoders */ /* Include the VFP and Neon decoders */
#include "translate-vfp.inc.c" #include "translate-vfp.c.inc"
#include "translate-neon.inc.c" #include "translate-neon.c.inc"
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
{ {
@@ -5217,10 +5217,10 @@ static int t16_pop_list(DisasContext *s, int x)
* Include the generated decoders. * Include the generated decoders.
*/ */
#include "decode-a32.inc.c" #include "decode-a32.c.inc"
#include "decode-a32-uncond.inc.c" #include "decode-a32-uncond.c.inc"
#include "decode-t32.inc.c" #include "decode-t32.c.inc"
#include "decode-t16.inc.c" #include "decode-t16.c.inc"
/* Helpers to swap operands for reverse-subtract. */ /* Helpers to swap operands for reverse-subtract. */
static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b)
target/avr/Makefile.objs
+2 -2
View File
@@ -21,12 +21,12 @@
DECODETREE = $(SRC_PATH)/scripts/decodetree.py DECODETREE = $(SRC_PATH)/scripts/decodetree.py
decode-y = $(SRC_PATH)/target/avr/insn.decode decode-y = $(SRC_PATH)/target/avr/insn.decode
target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE) target/avr/decode_insn.c.inc: $(decode-y) $(DECODETREE)
$(call quiet-command, \ $(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/avr/translate.o: target/avr/decode_insn.inc.c target/avr/translate.o: target/avr/decode_insn.c.inc
obj-y += translate.o cpu.o helper.o obj-y += translate.o cpu.o helper.o
obj-y += gdbstub.o obj-y += gdbstub.o
target/avr/disas.c
+1 -1
View File
@@ -60,7 +60,7 @@ static int append_16(DisasContext *ctx, int x)
/* Include the auto-generated decoder. */ /* Include the auto-generated decoder. */
static bool decode_insn(DisasContext *ctx, uint16_t insn); static bool decode_insn(DisasContext *ctx, uint16_t insn);
#include "decode_insn.inc.c" #include "decode_insn.c.inc"
#define output(mnemonic, format, ...) \ #define output(mnemonic, format, ...) \
(pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \ (pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \

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