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hw/misc/xlnx-versal-crl: add the versal2 version
Add the versal2 version of the CRL device. For the implemented part, it is similar to the versal version but drives reset line of more devices. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-37-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel
committed by
Peter Maydell
Peter Maydell
parent
4707024bc3
commit
00580a9d71
@@ -10,6 +10,7 @@
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typedef enum VersalVersion {
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VERSAL_VER_VERSAL,
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VERSAL_VER_VERSAL2,
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} VersalVersion;
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#endif
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@@ -17,10 +17,12 @@
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#define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base"
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#define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
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#define TYPE_XLNX_VERSAL2_CRL "xlnx-versal2-crl"
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OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass,
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XLNX_VERSAL_CRL_BASE)
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersal2CRL, XLNX_VERSAL2_CRL)
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REG32(ERR_CTRL, 0x0)
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FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
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@@ -220,6 +222,314 @@ REG32(PSM_RST_MODE, 0x370)
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#define CRL_R_MAX (R_PSM_RST_MODE + 1)
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REG32(VERSAL2_ERR_CTRL, 0x0)
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REG32(VERSAL2_WPROT, 0x1c)
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FIELD(VERSAL2_WPROT, ACTIVE, 0, 1)
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REG32(VERSAL2_RPLL_CTRL, 0x40)
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FIELD(VERSAL2_RPLL_CTRL, POST_SRC, 24, 3)
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FIELD(VERSAL2_RPLL_CTRL, PRE_SRC, 20, 3)
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FIELD(VERSAL2_RPLL_CTRL, CLKOUTDIV, 16, 2)
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FIELD(VERSAL2_RPLL_CTRL, FBDIV, 8, 8)
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FIELD(VERSAL2_RPLL_CTRL, BYPASS, 3, 1)
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FIELD(VERSAL2_RPLL_CTRL, RESET, 0, 1)
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REG32(VERSAL2_RPLL_CFG, 0x44)
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FIELD(VERSAL2_RPLL_CFG, LOCK_DLY, 25, 7)
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FIELD(VERSAL2_RPLL_CFG, LOCK_CNT, 13, 10)
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FIELD(VERSAL2_RPLL_CFG, LFHF, 10, 2)
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FIELD(VERSAL2_RPLL_CFG, CP, 5, 4)
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FIELD(VERSAL2_RPLL_CFG, RES, 0, 4)
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REG32(VERSAL2_FLXPLL_CTRL, 0x50)
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FIELD(VERSAL2_FLXPLL_CTRL, POST_SRC, 24, 3)
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FIELD(VERSAL2_FLXPLL_CTRL, PRE_SRC, 20, 3)
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FIELD(VERSAL2_FLXPLL_CTRL, CLKOUTDIV, 16, 2)
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FIELD(VERSAL2_FLXPLL_CTRL, FBDIV, 8, 8)
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FIELD(VERSAL2_FLXPLL_CTRL, BYPASS, 3, 1)
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FIELD(VERSAL2_FLXPLL_CTRL, RESET, 0, 1)
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REG32(VERSAL2_FLXPLL_CFG, 0x54)
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FIELD(VERSAL2_FLXPLL_CFG, LOCK_DLY, 25, 7)
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FIELD(VERSAL2_FLXPLL_CFG, LOCK_CNT, 13, 10)
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FIELD(VERSAL2_FLXPLL_CFG, LFHF, 10, 2)
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FIELD(VERSAL2_FLXPLL_CFG, CP, 5, 4)
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FIELD(VERSAL2_FLXPLL_CFG, RES, 0, 4)
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REG32(VERSAL2_PLL_STATUS, 0x60)
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FIELD(VERSAL2_PLL_STATUS, FLXPLL_STABLE, 3, 1)
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FIELD(VERSAL2_PLL_STATUS, RPLL_STABLE, 2, 1)
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FIELD(VERSAL2_PLL_STATUS, FLXPLL_LOCK, 1, 1)
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FIELD(VERSAL2_PLL_STATUS, RPLL_LOCK, 0, 1)
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REG32(VERSAL2_RPLL_TO_XPD_CTRL, 0x100)
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FIELD(VERSAL2_RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
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REG32(VERSAL2_LPX_TOP_SWITCH_CTRL, 0x104)
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FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
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FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_LPX_LSBUS_CLK_CTRL, 0x108)
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FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_RPU_CLK_CTRL, 0x10c)
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FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERE, 24, 1)
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FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERD, 23, 1)
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FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERC, 22, 1)
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FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERB, 21, 1)
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FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERA, 20, 1)
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FIELD(VERSAL2_RPU_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_RPU_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_OCM_CLK_CTRL, 0x120)
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FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM3, 24, 1)
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FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM2, 23, 1)
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FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM1, 22, 1)
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FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM0, 21, 1)
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REG32(VERSAL2_IOU_SWITCH_CLK_CTRL, 0x124)
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FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_GEM0_REF_CTRL, 0x128)
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FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_RX, 27, 1)
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FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_TX, 26, 1)
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FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_GEM0_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_GEM0_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_GEM1_REF_CTRL, 0x12c)
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FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_RX, 27, 1)
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FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_TX, 26, 1)
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FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_GEM1_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_GEM1_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_GEM_TSU_REF_CLK_CTRL, 0x130)
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FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_USB0_BUS_REF_CLK_CTRL, 0x134)
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FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_USB1_BUS_REF_CLK_CTRL, 0x138)
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FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_UART0_REF_CLK_CTRL, 0x13c)
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FIELD(VERSAL2_UART0_REF_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_UART0_REF_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_UART0_REF_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_UART1_REF_CLK_CTRL, 0x140)
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FIELD(VERSAL2_UART1_REF_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_UART1_REF_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_UART1_REF_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_SPI0_REF_CLK_CTRL, 0x144)
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FIELD(VERSAL2_SPI0_REF_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_SPI0_REF_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_SPI0_REF_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_SPI1_REF_CLK_CTRL, 0x148)
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FIELD(VERSAL2_SPI1_REF_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_SPI1_REF_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_SPI1_REF_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_CAN0_REF_2X_CTRL, 0x14c)
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FIELD(VERSAL2_CAN0_REF_2X_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_CAN0_REF_2X_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_CAN0_REF_2X_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_CAN1_REF_2X_CTRL, 0x150)
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FIELD(VERSAL2_CAN1_REF_2X_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_CAN1_REF_2X_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_CAN1_REF_2X_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_CAN2_REF_2X_CTRL, 0x154)
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FIELD(VERSAL2_CAN2_REF_2X_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_CAN2_REF_2X_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_CAN2_REF_2X_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_CAN3_REF_2X_CTRL, 0x158)
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FIELD(VERSAL2_CAN3_REF_2X_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_CAN3_REF_2X_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_CAN3_REF_2X_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C0_REF_CTRL, 0x15c)
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FIELD(VERSAL2_I3C0_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C0_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C0_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C1_REF_CTRL, 0x160)
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FIELD(VERSAL2_I3C1_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C1_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C1_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C2_REF_CTRL, 0x164)
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FIELD(VERSAL2_I3C2_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C2_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C2_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C3_REF_CTRL, 0x168)
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FIELD(VERSAL2_I3C3_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C3_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C3_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C4_REF_CTRL, 0x16c)
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FIELD(VERSAL2_I3C4_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C4_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C4_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C5_REF_CTRL, 0x170)
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FIELD(VERSAL2_I3C5_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C5_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C5_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C6_REF_CTRL, 0x174)
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FIELD(VERSAL2_I3C6_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C6_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C6_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_I3C7_REF_CTRL, 0x178)
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FIELD(VERSAL2_I3C7_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_I3C7_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_I3C7_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_DBG_LPX_CTRL, 0x17c)
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FIELD(VERSAL2_DBG_LPX_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_DBG_LPX_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_DBG_LPX_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_TIMESTAMP_REF_CTRL, 0x180)
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FIELD(VERSAL2_TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_SAFETY_CHK, 0x184)
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REG32(VERSAL2_ASU_CLK_CTRL, 0x188)
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FIELD(VERSAL2_ASU_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_ASU_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_DBG_TSTMP_CLK_CTRL, 0x18c)
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FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_MMI_TOPSW_CLK_CTRL, 0x190)
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FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, CLKACT, 25, 1)
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FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_WWDT_PLL_CLK_CTRL, 0x194)
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FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, DIVISOR0, 8, 10)
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FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, SRCSEL, 0, 3)
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REG32(VERSAL2_RCLK_CTRL, 0x1a0)
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FIELD(VERSAL2_RCLK_CTRL, CLKACT, 8, 6)
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FIELD(VERSAL2_RCLK_CTRL, SELECT, 0, 6)
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REG32(VERSAL2_RST_RPU_A, 0x310)
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FIELD(VERSAL2_RST_RPU_A, TOPRESET, 16, 1)
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FIELD(VERSAL2_RST_RPU_A, CORE1_POR, 9, 1)
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FIELD(VERSAL2_RST_RPU_A, CORE0_POR, 8, 1)
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FIELD(VERSAL2_RST_RPU_A, CORE1_RESET, 1, 1)
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FIELD(VERSAL2_RST_RPU_A, CORE0_RESET, 0, 1)
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REG32(VERSAL2_RST_RPU_B, 0x314)
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FIELD(VERSAL2_RST_RPU_B, TOPRESET, 16, 1)
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FIELD(VERSAL2_RST_RPU_B, CORE1_POR, 9, 1)
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FIELD(VERSAL2_RST_RPU_B, CORE0_POR, 8, 1)
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FIELD(VERSAL2_RST_RPU_B, CORE1_RESET, 1, 1)
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FIELD(VERSAL2_RST_RPU_B, CORE0_RESET, 0, 1)
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REG32(VERSAL2_RST_RPU_C, 0x318)
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FIELD(VERSAL2_RST_RPU_C, TOPRESET, 16, 1)
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FIELD(VERSAL2_RST_RPU_C, CORE1_POR, 9, 1)
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FIELD(VERSAL2_RST_RPU_C, CORE0_POR, 8, 1)
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FIELD(VERSAL2_RST_RPU_C, CORE1_RESET, 1, 1)
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FIELD(VERSAL2_RST_RPU_C, CORE0_RESET, 0, 1)
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REG32(VERSAL2_RST_RPU_D, 0x31c)
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FIELD(VERSAL2_RST_RPU_D, TOPRESET, 16, 1)
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FIELD(VERSAL2_RST_RPU_D, CORE1_POR, 9, 1)
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FIELD(VERSAL2_RST_RPU_D, CORE0_POR, 8, 1)
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FIELD(VERSAL2_RST_RPU_D, CORE1_RESET, 1, 1)
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FIELD(VERSAL2_RST_RPU_D, CORE0_RESET, 0, 1)
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REG32(VERSAL2_RST_RPU_E, 0x320)
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FIELD(VERSAL2_RST_RPU_E, TOPRESET, 16, 1)
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FIELD(VERSAL2_RST_RPU_E, CORE1_POR, 9, 1)
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FIELD(VERSAL2_RST_RPU_E, CORE0_POR, 8, 1)
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FIELD(VERSAL2_RST_RPU_E, CORE1_RESET, 1, 1)
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FIELD(VERSAL2_RST_RPU_E, CORE0_RESET, 0, 1)
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REG32(VERSAL2_RST_RPU_GD_0, 0x324)
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FIELD(VERSAL2_RST_RPU_GD_0, RESET, 1, 1)
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FIELD(VERSAL2_RST_RPU_GD_0, TOP_RESET, 0, 1)
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REG32(VERSAL2_RST_RPU_GD_1, 0x328)
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FIELD(VERSAL2_RST_RPU_GD_1, RESET, 1, 1)
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FIELD(VERSAL2_RST_RPU_GD_1, TOP_RESET, 0, 1)
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REG32(VERSAL2_RST_ASU_GD, 0x32c)
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FIELD(VERSAL2_RST_ASU_GD, RESET, 1, 1)
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FIELD(VERSAL2_RST_ASU_GD, TOP_RESET, 0, 1)
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REG32(VERSAL2_RST_ADMA, 0x334)
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FIELD(VERSAL2_RST_ADMA, RESET, 0, 1)
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REG32(VERSAL2_RST_SDMA, 0x338)
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FIELD(VERSAL2_RST_SDMA, RESET, 0, 1)
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REG32(VERSAL2_RST_GEM0, 0x33c)
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FIELD(VERSAL2_RST_GEM0, RESET, 0, 1)
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REG32(VERSAL2_RST_GEM1, 0x340)
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FIELD(VERSAL2_RST_GEM1, RESET, 0, 1)
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REG32(VERSAL2_RST_USB0, 0x348)
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FIELD(VERSAL2_RST_USB0, RESET, 0, 1)
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REG32(VERSAL2_RST_USB1, 0x34c)
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FIELD(VERSAL2_RST_USB1, RESET, 0, 1)
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REG32(VERSAL2_RST_UART0, 0x350)
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FIELD(VERSAL2_RST_UART0, RESET, 0, 1)
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REG32(VERSAL2_RST_UART1, 0x354)
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FIELD(VERSAL2_RST_UART1, RESET, 0, 1)
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REG32(VERSAL2_RST_SPI0, 0x358)
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FIELD(VERSAL2_RST_SPI0, RESET, 0, 1)
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REG32(VERSAL2_RST_SPI1, 0x35c)
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FIELD(VERSAL2_RST_SPI1, RESET, 0, 1)
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REG32(VERSAL2_RST_CAN0, 0x360)
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FIELD(VERSAL2_RST_CAN0, RESET, 0, 1)
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REG32(VERSAL2_RST_CAN1, 0x364)
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FIELD(VERSAL2_RST_CAN1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_CAN2, 0x368)
|
||||
FIELD(VERSAL2_RST_CAN2, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_CAN3, 0x36c)
|
||||
FIELD(VERSAL2_RST_CAN3, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C0, 0x374)
|
||||
FIELD(VERSAL2_RST_I3C0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C1, 0x378)
|
||||
FIELD(VERSAL2_RST_I3C1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C2, 0x37c)
|
||||
FIELD(VERSAL2_RST_I3C2, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C3, 0x380)
|
||||
FIELD(VERSAL2_RST_I3C3, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C4, 0x384)
|
||||
FIELD(VERSAL2_RST_I3C4, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C5, 0x388)
|
||||
FIELD(VERSAL2_RST_I3C5, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C6, 0x38c)
|
||||
FIELD(VERSAL2_RST_I3C6, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_I3C7, 0x390)
|
||||
FIELD(VERSAL2_RST_I3C7, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_DBG_LPX, 0x398)
|
||||
FIELD(VERSAL2_RST_DBG_LPX, RESET_HSDP, 1, 1)
|
||||
FIELD(VERSAL2_RST_DBG_LPX, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_GPIO, 0x39c)
|
||||
FIELD(VERSAL2_RST_GPIO, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_TTC, 0x3a0)
|
||||
FIELD(VERSAL2_RST_TTC, TTC7_RESET, 7, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC6_RESET, 6, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC5_RESET, 5, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC4_RESET, 4, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC3_RESET, 3, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC2_RESET, 2, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC1_RESET, 1, 1)
|
||||
FIELD(VERSAL2_RST_TTC, TTC0_RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_TIMESTAMP, 0x3a4)
|
||||
FIELD(VERSAL2_RST_TIMESTAMP, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT0, 0x3a8)
|
||||
FIELD(VERSAL2_RST_SWDT0, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT1, 0x3ac)
|
||||
FIELD(VERSAL2_RST_SWDT1, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT2, 0x3b0)
|
||||
FIELD(VERSAL2_RST_SWDT2, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT3, 0x3b4)
|
||||
FIELD(VERSAL2_RST_SWDT3, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SWDT4, 0x3b8)
|
||||
FIELD(VERSAL2_RST_SWDT4, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_IPI, 0x3bc)
|
||||
FIELD(VERSAL2_RST_IPI, RESET, 0, 1)
|
||||
REG32(VERSAL2_RST_SYSMON, 0x3c0)
|
||||
FIELD(VERSAL2_RST_SYSMON, CFG_RST, 0, 1)
|
||||
REG32(VERSAL2_ASU_MB_RST_MODE, 0x3c4)
|
||||
FIELD(VERSAL2_ASU_MB_RST_MODE, WAKEUP, 2, 1)
|
||||
FIELD(VERSAL2_ASU_MB_RST_MODE, RST_MODE, 0, 2)
|
||||
REG32(VERSAL2_FPX_TOPSW_MUX_CTRL, 0x3c8)
|
||||
FIELD(VERSAL2_FPX_TOPSW_MUX_CTRL, SELECT, 0, 1)
|
||||
REG32(VERSAL2_RST_FPX, 0x3d0)
|
||||
FIELD(VERSAL2_RST_FPX, SRST, 1, 1)
|
||||
FIELD(VERSAL2_RST_FPX, POR, 0, 1)
|
||||
REG32(VERSAL2_RST_MMI, 0x3d4)
|
||||
FIELD(VERSAL2_RST_MMI, POR, 0, 1)
|
||||
REG32(VERSAL2_RST_OCM, 0x3d8)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM3, 3, 1)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM2, 2, 1)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM1, 1, 1)
|
||||
FIELD(VERSAL2_RST_OCM, RESET_OCM0, 0, 1)
|
||||
|
||||
#define VERSAL2_CRL_R_MAX (R_VERSAL2_RST_OCM + 1)
|
||||
|
||||
struct XlnxVersalCRLBase {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
@@ -249,11 +559,30 @@ struct XlnxVersalCRL {
|
||||
RegisterInfo regs_info[CRL_R_MAX];
|
||||
};
|
||||
|
||||
struct XlnxVersal2CRL {
|
||||
XlnxVersalCRLBase parent_obj;
|
||||
|
||||
struct {
|
||||
DeviceState *rpu[10];
|
||||
DeviceState *adma[8];
|
||||
DeviceState *sdma[8];
|
||||
DeviceState *uart[2];
|
||||
DeviceState *gem[2];
|
||||
DeviceState *usb[2];
|
||||
DeviceState *can[4];
|
||||
} cfg;
|
||||
|
||||
RegisterInfo regs_info[VERSAL2_CRL_R_MAX];
|
||||
uint32_t regs[VERSAL2_CRL_R_MAX];
|
||||
};
|
||||
|
||||
static inline const char *xlnx_versal_crl_class_name(VersalVersion ver)
|
||||
{
|
||||
switch (ver) {
|
||||
case VERSAL_VER_VERSAL:
|
||||
return TYPE_XLNX_VERSAL_CRL;
|
||||
case VERSAL_VER_VERSAL2:
|
||||
return TYPE_XLNX_VERSAL2_CRL;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user