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Commit Graph

  • 52cefeb5c3 Merge pull request #17798 from unknownbrackets/irjit-vf2ix Henrik Rydgård 2023-07-30 09:08:45 +02:00
  • 88bef1b00f Merge pull request #17803 from Narugakuruga/patch-24 Henrik Rydgård 2023-07-30 09:06:45 +02:00
  • 0036f3c494 riscv: Implement FMin/FMax. Unknown W. Brackets 2023-07-29 13:48:27 -07:00
  • 8e8081c686 riscv: Implement VFPU compares. Unknown W. Brackets 2023-07-29 12:48:20 -07:00
  • 9c9330a207 riscv: Implement float conditional move. Unknown W. Brackets 2023-07-29 11:05:21 -07:00
  • 70ff18a463 riscv: Implement count leading zeros. Unknown W. Brackets 2023-07-29 10:53:16 -07:00
  • a5671bc716 riscv: Add simple debug log of missed ops. Unknown W. Brackets 2023-07-29 10:44:57 -07:00
  • 99d5a90898 Update zh_CN.ini Narugakuruga 2023-07-30 14:23:21 +08:00
  • ec4927069e 1. remove some unused code 2. add some missing header 3. fix error address offset operation haorui wang 2023-07-30 12:31:31 +08:00
  • 6aa4b0c5e1 irjit: Fix vmin/vmax nan handling. Unknown W. Brackets 2023-07-29 19:13:12 -07:00
  • 6d4fb949c2 riscv: Implement float compare ops. Unknown W. Brackets 2023-07-29 10:28:00 -07:00
  • 6b632a103d riscv: Implement FSin/similar. Unknown W. Brackets 2023-07-29 08:02:41 -07:00
  • 921bd2391c riscv: Implement vi2s. Unknown W. Brackets 2023-07-29 07:50:06 -07:00
  • e2765db4dc riscv: Implement division. Unknown W. Brackets 2023-07-29 07:42:36 -07:00
  • f65b6fdb20 riscv: Remove incomplete block check. Unknown W. Brackets 2023-07-27 22:23:47 -07:00
  • 8d60c10a64 riscv: Use jit address offsets directly. Unknown W. Brackets 2023-07-27 22:23:06 -07:00
  • b6d2e64aca Debugger: Fix disasm of ll/sc. Unknown W. Brackets 2023-07-29 18:50:09 -07:00
  • 9a8ac1fe08 x86jit: Implement ll/sc. Unknown W. Brackets 2023-07-29 18:49:45 -07:00
  • e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. Unknown W. Brackets 2023-07-29 18:15:49 -07:00
  • a5a2671af3 irjit: Implement vf2ix. Unknown W. Brackets 2023-07-29 11:57:30 -07:00
  • f0d4267c5e HLE: Reset ll/sc link on any syscall. Unknown W. Brackets 2023-07-29 17:51:52 -07:00
  • df2462b1d9 irjit: Implement ll/sc. Unknown W. Brackets 2023-07-29 17:51:16 -07:00
  • 48586ed0ad irjit: Combine Load32Left/Right even on unaligned. Unknown W. Brackets 2023-07-27 23:28:19 -07:00
  • b473f1e649 Merge pull request #17780 from hch12907/sdl-ttf Henrik Rydgård 2023-07-29 22:51:27 +02:00
  • 4062aa5687 Merge pull request #17795 from styxnix/master Henrik Rydgård 2023-07-29 20:21:23 +02:00
  • c2e6ec7f7e Update fi_FI.ini Jaakko Saarikko 2023-07-29 17:15:50 +03:00
  • aaa7e90174 SDL: fix a curious crash Hoe Hao Cheng 2023-07-28 21:33:19 +08:00
  • 1c890be702 Use common UTF8 infrastructure instead of rewriting one Hoe Hao Cheng 2023-07-28 21:00:09 +08:00
  • f88d1a287e SDL: implement font fallback for TextDrawerSDL Hoe Hao Cheng 2023-07-25 21:57:39 +08:00
  • 56c2974e5e Merge pull request #17793 from warmenhoven/dev/warmenhoven/libretro-apple Henrik Rydgård 2023-07-28 11:32:54 +02:00
  • c19aa05b60 Fix libretro build on apple platforms Eric Warmenhoven 2023-07-28 03:37:07 -04:00
  • 4aa2b1fcac Merge pull request #17783 from unknownbrackets/riscv-jit Henrik Rydgård 2023-07-28 08:38:19 +02:00
  • a181f6d5b8 riscv: Add a comment for FMUL testing later. Unknown W. Brackets 2023-07-27 22:16:29 -07:00
  • bf40eae4f8 Merge pull request #17789 from styxnix/master Henrik Rydgård 2023-07-27 16:54:03 +02:00
  • 7e333b8c4e Merge pull request #17790 from Saramagrean/patch-5 Henrik Rydgård 2023-07-27 16:48:58 +02:00
  • 92b6613adf Update th_TH.ini Benjamin Benda Gates 2023-07-27 18:42:56 +07:00
  • 4789656b33 Update fi_FI.ini Jaakko Saarikko 2023-07-26 22:44:55 +03:00
  • 982ce968ea Merge pull request #17785 from hrydgard/naett-ndk-build-fix Unknown W. Brackets 2023-07-25 22:58:48 -07:00
  • e478dbff3d Merge pull request #17784 from unknownbrackets/arm64-round Henrik Rydgård 2023-07-26 07:32:06 +02:00
  • 2f2878687f Merge pull request #17782 from unknownbrackets/net-cancel Henrik Rydgård 2023-07-26 07:30:28 +02:00
  • ce45c943be Bump naett with fix for build problem on newer NDK Henrik Rydgård 2023-07-26 07:28:25 +02:00
  • 5122b0c78e riscv: Cleanup unnecessary fcr31 func. Unknown W. Brackets 2023-07-25 19:58:31 -07:00
  • 0c9dce8ba8 riscv: Implement vec4 dot. Unknown W. Brackets 2023-07-25 19:12:17 -07:00
  • 23e9dffc68 riscv: Implement vec4 shuffle and init. Unknown W. Brackets 2023-07-25 19:12:00 -07:00
  • 4e17c59cc2 riscv: Implement simple vec4 ops via floats. Unknown W. Brackets 2023-07-25 19:11:27 -07:00
  • df313bd296 riscv: Fix rounding mode setting. Unknown W. Brackets 2023-07-25 00:37:39 -07:00
  • 9157d992ac jit-ir: Implement cfc1/ctc1. Unknown W. Brackets 2016-05-15 19:58:40 -07:00
  • ca7a520a19 riscv: Implement FMul. Unknown W. Brackets 2023-07-24 22:59:08 -07:00
  • 9a9b371856 riscv: Implement FSign using FCLASS. Unknown W. Brackets 2023-07-24 22:58:40 -07:00
  • 05360d5c7a riscv: Implement simplest float ops. Unknown W. Brackets 2023-07-24 22:58:23 -07:00
  • bb6fdd0246 riscv: Add floating point load/stores. Unknown W. Brackets 2023-07-24 22:56:55 -07:00
  • 7071884a47 riscv: Handle rounding mode and ctrl transfers. Unknown W. Brackets 2023-07-24 20:49:40 -07:00
  • 067a033dc0 riscv: Add FPU regcache. Unknown W. Brackets 2023-07-24 20:48:17 -07:00
  • c3db3d5187 arm64jit: When rouding unset, use nearest. Unknown W. Brackets 2023-07-25 20:30:05 -07:00
  • 94f7231e73 net: Fix request cancelling. Unknown W. Brackets 2023-07-25 19:37:28 -07:00
  • 8f404a1961 softgpu: Fix minor typo. Unknown W. Brackets 2023-07-25 19:12:27 -07:00
  • a8edf5fa24 riscv: Reduce bloat in jit fallbacks. Unknown W. Brackets 2023-07-23 23:52:50 -07:00
  • b97b7f3663 riscv: Make some regcache methods private. Unknown W. Brackets 2023-07-23 23:03:59 -07:00
  • f229573bb2 Merge pull request #16251 from gucio321/fix-wayland-vulkan Henrik Rydgård 2023-07-25 09:52:43 +02:00
  • 3383d5b93a Merge pull request #17751 from unknownbrackets/riscv-jit Unknown W. Brackets 2023-07-25 00:42:22 -07:00
  • 2b826b5614 SDL: implement TextDrawer using SDL2_ttf Hoe Hao Cheng 2023-07-25 12:55:23 +08:00
  • f3c89e49f0 Merge pull request #17778 from hrydgard/new-icons Henrik Rydgård 2023-07-24 15:49:38 +02:00
  • fecd0b8cd7 Use the new play button icon in the retroachievement sound customizer Henrik Rydgård 2023-07-24 14:56:35 +02:00
  • 2baba83f1a Add a bunch of new icon images to the atlas. Henrik Rydgård 2023-07-24 14:39:40 +02:00
  • 3c2f67a097 Merge pull request #17777 from hrydgard/fix-achievements-from-frontend Henrik Rydgård 2023-07-24 12:37:40 +02:00
  • a72c4aa383 Actually fix the race condition. Can't do any initialization step while waiting. Henrik Rydgård 2023-07-24 12:08:15 +02:00
  • 3ae520c35d RetroAchievements: Fix another race condition, improve logging. Henrik Rydgård 2023-07-24 12:00:16 +02:00
  • bee2400230 Merge pull request #17769 from unknownbrackets/vertexjit-debug Henrik Rydgård 2023-07-24 09:39:52 +02:00
  • c697dca3e0 Merge pull request #17776 from unknownbrackets/riscv-vertexjit Henrik Rydgård 2023-07-24 09:13:17 +02:00
  • b6f83ca969 riscv: Cleanup some pointerification flags. Unknown W. Brackets 2023-07-23 21:17:39 -07:00
  • 18c48681a8 riscv: Implement multiply instructions. Unknown W. Brackets 2023-07-23 17:09:05 -07:00
  • 7f4689e8fa riscv: Use direct SLI/SLIU instructions. Unknown W. Brackets 2023-07-23 16:24:49 -07:00
  • ca15fa7061 riscv: Enable jit by default. Unknown W. Brackets 2023-07-23 14:20:57 -07:00
  • 4100767b5e riscv: Optimize SetConst a bit. Unknown W. Brackets 2023-07-23 09:52:05 -07:00
  • f7f7531500 riscv: Fix min/max normalization. Unknown W. Brackets 2023-07-23 09:48:44 -07:00
  • 34bfe93ea5 riscv: Fix block lookup issues. Unknown W. Brackets 2023-07-23 08:15:15 -07:00
  • 92694e765f riscv: Implement conditional moves. Unknown W. Brackets 2023-07-22 22:34:48 -07:00
  • 2c7da94bd1 riscv: Implement shifts and compares. Unknown W. Brackets 2023-07-22 22:08:28 -07:00
  • 5ed2f0d559 riscv: Implement logic ops. Unknown W. Brackets 2023-07-22 19:08:28 -07:00
  • 94be343591 riscv: Try to keep regs normalized, track. Unknown W. Brackets 2023-07-22 18:32:43 -07:00
  • 7aafa11d24 riscv: Implement conditional exits. Unknown W. Brackets 2023-07-22 14:29:38 -07:00
  • 8ee73264bf riscv: Correct depointerify on FlushAll(). Unknown W. Brackets 2023-07-22 14:12:32 -07:00
  • 720f868a10 riscv: Use R_RA as a temporary for calls. Unknown W. Brackets 2023-07-22 13:47:44 -07:00
  • 76e3246065 riscv: Reduce jit codesize a bit. Unknown W. Brackets 2023-07-22 00:30:29 -07:00
  • d31eded9ba riscv: Allow dirty pointers, explicitly. Unknown W. Brackets 2023-07-21 23:38:20 -07:00
  • 624caa2dea riscv: Implement the simplest exits. Unknown W. Brackets 2023-07-21 23:09:34 -07:00
  • 1dfedde741 riscv: Avoid needless save/load around compile. Unknown W. Brackets 2023-07-21 23:09:06 -07:00
  • 165169eb31 riscv: Implement load and store ops. Unknown W. Brackets 2023-07-21 20:32:47 -07:00
  • c2da7d18bb riscv: Stub out more IR compilation categories. Unknown W. Brackets 2023-07-21 20:29:35 -07:00
  • 05a2789cf4 riscv: Implement some simple assign instructions. Unknown W. Brackets 2023-07-20 23:55:45 -07:00
  • c6c25af484 riscv: Add some safety to pointerifying. Unknown W. Brackets 2023-07-20 23:37:34 -07:00
  • bf7a6eb2cd riscv: Add jit for some initial instructions. Unknown W. Brackets 2023-07-20 21:09:59 -07:00
  • 4c1cc2dfdc riscv: Add a register cache for jit. Unknown W. Brackets 2023-07-20 19:22:12 -07:00
  • b2d3c750f1 irjit: Define a specific IRReg type. Unknown W. Brackets 2023-07-20 19:21:00 -07:00
  • 47b81985bd riscv: Initial untested dispatcher. Unknown W. Brackets 2023-07-17 23:28:43 -07:00
  • e271e43ec5 riscv: Initial staffolding for IR based jit. Unknown W. Brackets 2023-07-16 18:54:59 -07:00
  • 3468423bb4 Debugger: Handle missing crash/block ptrs better. Unknown W. Brackets 2023-07-16 18:51:20 -07:00
  • b041e712de riscv: Fix signed position bug in vertexjit. Unknown W. Brackets 2023-07-23 17:55:07 -07:00
  • 5cbad1982b riscv: Correct 565 morph mistake. Unknown W. Brackets 2023-07-23 17:54:22 -07:00
  • b7bcba16c8 Merge pull request #17774 from GABO1423/ppsspp-en-español Henrik Rydgård 2023-07-24 01:51:28 +02:00