Henrik Rydgård
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e90f7f360d
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Merge pull request #4480 from unknownbrackets/perf
Flush regs using STMIA if possible, plus imm adjustments (armjit)
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2013-11-09 08:41:25 -08:00 |
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Henrik Rydgard
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06ce01ea04
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Remove erroneous comment.
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2013-11-09 17:34:52 +01:00 |
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Unknown W. Brackets
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54168b173e
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armjit: Clean up some magic numbers.
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2013-11-09 08:25:08 -08:00 |
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Unknown W. Brackets
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6038d96b46
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armjit: Flush regs using STMIA where possible.
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2013-11-09 08:25:07 -08:00 |
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Unknown W. Brackets
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e686ff59bf
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armjit: Allocate regs in preferred slots.
This may allow better flushing. Not sure if these are the best regs,
but if they aren't it shouldn't really hurt.
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2013-11-09 08:25:07 -08:00 |
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Unknown W. Brackets
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cb3bb73148
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armjit: Improve GPR typesafety.
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2013-11-09 08:24:15 -08:00 |
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Unknown W. Brackets
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945b8bf5c5
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armjit: optimize reverse subtract, avoid temp imms.
If we have a non-op2 imm, get rid of it asap. If we have a op2 friendly
imm, keep it.
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2013-11-09 08:18:43 -08:00 |
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Unknown W. Brackets
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415f22ecac
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armjit: Preserve imms on min/max as well.
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2013-11-09 08:18:43 -08:00 |
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Henrik Rydgard
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502f772856
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Add experimental mode to cache pointers in the arm jit.
Turned off for now as it needs more work but seems quite promising already.
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2013-11-09 17:15:30 +01:00 |
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Henrik Rydgard
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58c39a38ee
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ARM regcache: Add mechanism to keep registers converted to pointers around
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2013-11-09 16:57:29 +01:00 |
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Henrik Rydgard
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5ad04a23f4
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x86 jit: Rename BindToRegister to MapReg
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2013-11-09 15:23:31 +01:00 |
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Henrik Rydgard
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d26692ef92
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Fix bug from a couple of commits ago in ARMJit
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2013-11-09 15:22:39 +01:00 |
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Henrik Rydgard
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316d23d4cc
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Optimize mfv/mtv/mfc1/mtc1 on x86 too
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2013-11-09 14:06:45 +01:00 |
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Henrik Rydgard
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04451623b9
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This variant didn't seem to make much difference either (see prev commit)
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2013-11-09 13:06:10 +01:00 |
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Henrik Rydgard
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15bc5a8db7
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Add small ARM perf experiment. Did not help on ARMv7 so turned it off.
xsacha might want to try it on ARMv6.
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2013-11-09 12:57:07 +01:00 |
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Henrik Rydgard
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2fe898cda8
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Add comment with link to important github thread about sceSas threading
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2013-11-09 02:05:28 +01:00 |
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Unknown W. Brackets
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5d46a82f43
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armjit: Use a MOV for add/or with 0.
Might skip the ALU, so might be faster.
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2013-11-08 11:41:57 -08:00 |
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Unknown W. Brackets
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b8e126e7ce
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armjit: Preserve imms in slt/sltu as possible.
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2013-11-08 11:41:57 -08:00 |
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Unknown W. Brackets
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8393d4aaae
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armjit: Preserve immediates more in nor.
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2013-11-08 11:41:56 -08:00 |
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Unknown W. Brackets
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d7e42b26a3
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armjit: Avoid flushing imm on add t0, imm, imm.
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2013-11-08 11:41:56 -08:00 |
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Unknown W. Brackets
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a435c9dd13
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armjit: Optimize movz/movn with immediates.
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2013-11-08 11:41:55 -08:00 |
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Unknown W. Brackets
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376918c408
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armjit: Reverse add t0, N, t1 to preserve imm.
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2013-11-08 11:41:55 -08:00 |
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Unknown W. Brackets
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02dd250354
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armjit: Optimize out a few immediate logic cases.
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2013-11-08 11:39:24 -08:00 |
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Henrik Rydgard
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58db79672f
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Fix vmtvc on ARM, fixing issues with our prefix check. Add some logging.
Also improve vcmp on ARM.
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2013-11-08 19:59:11 +01:00 |
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Henrik Rydgard
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a028f07951
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Turn down some logging.
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2013-11-08 18:52:07 +01:00 |
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