18 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	fd38b10ab6	x86jit: Rename imm funcs to match armjit.	2013-11-10 21:59:49 -08:00
Henrik Rydgard	5ad04a23f4	x86 jit: Rename BindToRegister to MapReg	2013-11-09 15:23:31 +01:00
Unknown W. Brackets	95c68ae1e7	Assert some unlikely buffer overflows.	2013-10-26 18:30:55 -07:00
Unknown W. Brackets	2751da1cec	Cut down on work in regcache init on x86. ... Very tiny tiny optimization for games, but 8-10% optimization for tests.	2013-09-19 00:29:50 -07:00
Henrik Rydgard	324cde5a79	Let's actually use the log category mechanism. A first step.	2013-09-07 21:19:21 +02:00
Unknown W. Brackets	97aa1a631e	Improve typesafety in the x86 regalloc.	2013-08-24 19:41:10 -07:00
Unknown W. Brackets	64c2ea86c0	Add a method to save the gpr/fpr state in jit.	2013-08-16 00:12:49 -07:00
Henrik Rydgard	3b9e6243eb	Only flush the required registers on function calls (only implemented for real on ARM)	2013-07-28 22:21:43 +02:00
Unknown W. Brackets	2d15eb2acd	Re-enable lwl/lwr/swl/swr on the x86 jit. ... Now correctly handling ECX on x64.	2013-07-06 01:21:52 -07:00
Unknown W. Brackets	64c42ffaf2	Fix some warnings generated by clang.	2013-02-24 10:23:31 -08:00
Henrik Rydgard	68991511ee	Split out the FPU reg cache into its own file too.	2013-01-26 01:34:19 +01:00
Henrik Rydgard	ad5e2b58c6	Separate the two regcaches before doing major surgery to FPURegCache.	2013-01-26 01:34:18 +01:00
Unknown W. Brackets	ce5f393fb8	Hit immediates in the ALU better and more simply.	2013-01-25 00:16:55 -08:00
Unknown W. Brackets	df06bb5624	Add some checks to make sure ZERO is never set.	2013-01-20 19:48:53 -08:00
Henrik Rydgard	93470e0c1f	Remove some old PowerPC references...	2013-01-05 19:52:11 +01:00
Henrik Rydgård	ed68dea0d5	JIT: Ignore branches in delay slots. Not sure if this is 100% correct.	2012-12-26 08:37:53 +01:00
Henrik Rydgard	64cc573703	Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK.	2012-11-04 23:24:00 +01:00
Henrik Rydgard	4f7ad15758	Add snapshot of the whole source code.	2012-11-01 16:19:01 +01:00