Henrik Rydgard
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e809e39681
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Mips interpreter: Use unions instead of ugly casts. Strict-aliasing builds now work, but needs more testing so I don't enable it yet. Also some aliasing fixes for TransformPipeline.
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2013-06-11 21:44:37 +02:00 |
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Henrik Rydgard
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c5c3189436
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Fix some framebuffer-related crash bugs. Ignore cache instruction 'FILL'.
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2013-04-27 20:06:31 +02:00 |
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Henrik Rydgard
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06679fcce6
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Switch to homemade isinf/isnan implementations.
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2013-04-13 21:51:38 +02:00 |
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raven02
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39c3cf8744
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Ignore MIPS break error
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2013-04-09 16:13:24 +08:00 |
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niepodam
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94c2f0cd9d
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Fix build with gcc 4.8.0
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2013-04-04 19:16:15 +02:00 |
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Henrik Rydgard
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5293c152c6
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Untested support for Android-x86. No idea if this actually works.
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2013-03-21 20:52:33 +01:00 |
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Henrik Rydgard
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062c975b46
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Ignore cache function 24.
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2013-03-04 23:51:19 +01:00 |
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Unknown W. Brackets
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ac1209204c
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Add some reporting for CPU related stuff.
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2013-03-04 00:01:41 -08:00 |
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Henrik Rydgard
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516ca8a0c4
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Merge branch 'master' into armjit-fpu
Conflicts:
Core/MIPS/ARM/ArmJit.h
Core/MIPS/x86/CompVFPU.cpp
GPU/GLES/Framebuffer.cpp
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2013-02-28 23:56:28 +01:00 |
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Unknown W. Brackets
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2164a7fdf9
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Keep track of whether we're in the runloop or not.
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2013-02-23 13:01:00 -08:00 |
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Unknown W. Brackets
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08923c092b
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Implement ins and ext in the x86 jit.
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2013-02-21 01:25:01 -08:00 |
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Unknown W. Brackets
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2bdc9dc491
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Reset llBit on thread switch.
Never actually seen ll used, though... but this way it should
work as advertized, as long as a syscall doesn't happen in between...
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2013-02-20 12:09:13 -08:00 |
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Unknown W. Brackets
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3a365fef64
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Protect against some writes to $0.
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2013-02-20 12:09:12 -08:00 |
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Henrik Rydgard
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44e4ba8772
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Merge branch 'master' into armjit-fpu
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2013-02-15 21:42:44 +01:00 |
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Unknown W. Brackets
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abe390e6f3
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Add some checks for fpu/vfpu writing to $0.
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2013-02-14 00:27:09 -08:00 |
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Henrik Rydgard
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b0c160fa93
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Fix armjit fpu load / store
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2013-02-13 21:07:06 +01:00 |
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Unknown W. Brackets
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19cc652a37
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Correct NaN handling in fpu comparisons.
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2013-02-13 01:54:07 -08:00 |
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Unknown W. Brackets
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3cab6986c5
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Jit the FPU comparisons on x86.
Probably not too fast. Also, NaN handling seems wrong?
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2013-02-13 00:55:10 -08:00 |
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Unknown W. Brackets
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44b5adeaac
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Properly jit the break instruction.
Otherwise, it just keeps on going past it.
We never want to hit this anyway, but it's good to know if we do.
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2013-02-01 00:49:14 -08:00 |
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Henrik Rydgard
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29f1ae5f70
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add skeleton implementation of "cache" instruction
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2013-01-22 22:03:41 +01:00 |
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Unknown W. Brackets
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c324983340
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Make the jit support bltzal and friends.
Fixes problems with jit in games. Android changes completely untested.
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2013-01-22 08:04:01 -08:00 |
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Unknown W. Brackets
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d99d060c2e
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Decrement downcount in skipped likely slots.
Pretty sure this is right, it eats up a cycle as a nop.
Also some funny indentation.
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2013-01-21 19:00:09 -08:00 |
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Henrik Rydgard
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8915677241
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More progress but it weirds out...
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2013-01-08 21:24:42 +01:00 |
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Arthur Blot
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decbf9da81
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Fixed interpreter
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2013-01-03 17:01:12 +01:00 |
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Arthur Blot
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be91ad2f9c
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Fixed $zr being non-zero after loading instruction
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2013-01-03 16:14:45 +01:00 |
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