Henrik Rydgård
ed776d8c0b
ARM: Delete obsolete comments and check
2017-08-18 13:48:11 +02:00
Florent Castelli
8c3552de74
cmake: Detect features at compile time
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Instead of relying on manually passed down flags from CMake,
we now have ppsspp_config.h file to create the platform defines for us.
This improves support for multiplatform builds (such as iOS).
2016-10-19 12:31:19 +02:00
Henrik Rydgard
dc2f6a30fb
ARM64: Fix joining of lwl/lwr and swl/swr. "implement" the cache instruction.
2015-07-11 16:25:22 +02:00
Henrik Rydgård
a897723e6a
Separate out jit reading nearby instructions.
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This makes it easier to use an IR for these things, or remove them.
2015-04-11 00:53:24 -07:00
Henrik Rydgard
05a8e2e35d
Some work towards being able to build two JITs together
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This will be useful for testing/debugging, but not there yet.
2014-12-13 21:13:54 +01:00
Henrik Rydgard
51d55bd645
Namespacing cleanup (it's bad to do "using namespace" in a header)
2014-12-07 14:44:15 +01:00
Henrik Rydgard
4457dca4c9
Rename the ARM Jit class to ArmJit
2014-12-07 14:25:22 +01:00
Unknown W. Brackets
f6f943de63
jit: MAP_NOINIT should always mean MAP_DIRTY.
2014-11-29 00:14:08 -08:00
Unknown W. Brackets
5a89c17cf0
armjit: Allow R1 in regalloc, use LR as temp.
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LR should be safe, although it may make stack traces not work within jit,
they don't really tend to work anyway.
2014-03-28 18:38:38 -07:00
Unknown W. Brackets
ca0a8d0269
armjit: fix lwl/lwr from an imm address.
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Can't skip loading the reg value. Likely cause of #5057 , possibly other
bugs as well.
2014-03-13 00:23:00 -07:00
Henrik Rydgård
b2260149ae
ARM Jit: Avoid materializing some unnecessary immediates in loads/stores
2014-03-03 14:33:22 +01:00
Henrik Rydgard
5a02ea9ff4
Fix cache instruction on ARM
2013-12-10 13:26:32 +01:00
Unknown W. Brackets
98fb2e0402
armjit: Refer to R11 as MEMBASEREG for clarity.
2013-11-14 23:37:48 -08:00
Unknown W. Brackets
67eaa2fd1c
armjit: Optimize immediate load/stores in a row.
2013-11-10 16:32:48 -08:00
Unknown W. Brackets
7e46ee0b0f
armjit: Replace MOVI2R with using the regcache.
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So that it can optimize the value with existing imms.
Not actually optimizing yet.
2013-11-10 15:50:45 -08:00
Unknown W. Brackets
455a7e090d
Compile the cache instruction to nothing.
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Was showing up in a few profiles, does nothing currently.
2013-11-10 14:38:10 -08:00
Unknown W. Brackets
b2c2a87511
Fix omitted CC_AL reset, fixes #4498 .
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Was breaking non-fastmem lwl/lwr/etc.
2013-11-10 09:24:40 -08:00
Unknown W. Brackets
3aa8706ae7
armjit: Optimize lwl/lwr against an imm address.
2013-11-09 08:43:48 -08:00
Unknown W. Brackets
4026944b02
armjit: Handle lwl/lwr (not pretty, though.)
2013-11-09 08:42:30 -08:00
Unknown W. Brackets
cb3bb73148
armjit: Improve GPR typesafety.
2013-11-09 08:24:15 -08:00
Henrik Rydgard
502f772856
Add experimental mode to cache pointers in the arm jit.
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Turned off for now as it needs more work but seems quite promising already.
2013-11-09 17:15:30 +01:00
Henrik Rydgard
309f904c0c
Extract JitState into its own header (arm/x86)
2013-11-08 18:51:52 +01:00
Henrik Rydgard
32c95af820
ARM: Some zero-register fixes
2013-11-07 15:29:13 +01:00
Unknown W. Brackets
157b682344
Always use fastmem for sw/lw on SP.
2013-09-07 22:44:18 -07:00
Unknown W. Brackets
97aa1a631e
Improve typesafety in the x86 regalloc.
2013-08-24 19:41:10 -07:00
