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112 Commits

Author SHA1 Message Date
Henrik Rydgård
e51c58716b Fix minor code issues flagged by PVS-Studio and reported by alphrixus. 2024-10-10 14:10:30 +02:00
Henrik Rydgård
e01ca5b057 Logging API change (refactor) (#19324) 
* Rename LogType to Log

* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.

* Mac/ARM64 buildfix

* Do the same with the hle result log macros

* Rename the log names to mixed case while at it.

* iOS buildfix

* Qt buildfix attempt, ARM32 buildfix
 2024-07-14 14:42:59 +02:00
Henrik Rydgård
5bfc0259be Optimize away the redundant vector loads in the Wipeout games. 2024-06-08 23:22:58 +02:00
Henrik Rydgård
c9ca3904d3 Combine move-from-gpr and float cast. 2024-06-08 22:59:48 +02:00
Henrik Rydgård
0abcd00372 IR Interpreter: Don't split up lone lwr/swr/lwl/swl instructions, the interpreter handles them faster. 2024-06-08 22:28:11 +02:00
Henrik Rydgård
0c246297d2 Create an IR op for a FPRtoGPR + shift-right-8, very common 2024-06-07 21:26:20 +02:00
Henrik Rydgård
bd0beb68a4 Add new IR optimization pass, OptimizeLoadsAfterStores 2024-06-07 19:32:37 +02:00
Henrik Rydgård
da88011805 Specialize a few arithmetic instructions for the interpreter. 2024-06-07 19:32:37 +02:00
Henrik Rydgård
bdf7f5f40f IRInterpreter: Fix issue where we could accidentally optimize out CallReplacement ops. 2024-05-26 00:12:48 +02:00
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5e813e6bd6 irjit: Correct bad Vec4 overlap handling. 2023-10-14 20:54:40 -07:00
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cd46f0b4cb irjit: Cache IR metadata lookups. 
This improves compilation performance, because all those lookups were
adding up.
 2023-09-30 15:56:53 -07:00
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69b8fb9bc2 irjit: Correct alignment checks against SP. 2023-09-23 13:15:06 -07:00
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739e474957 irjit: Improve dot and store vec4 interaction. 2023-09-01 22:35:59 -07:00
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2ca638868c irjit: Remove Vec4Scale/Vec4Dot aliasing in pass. 2023-09-01 22:35:59 -07:00
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96c90c19c6 irjit: Reduce unnecessary shuffles. 
If it's never used as a Vec4 again, it's often not worth it.
 2023-09-01 22:35:59 -07:00
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5f84887dea irjit: Add a pass to keep Vec4s in Vec4s. 2023-09-01 22:35:59 -07:00
Henrik Rydgård
ae0af175de Merge pull request #18004 from unknownbrackets/x86-jit-minor 
x86jit: Small cleanup and tweaks, downcountInRegster, GetFPRLaneCount bugfix
 2023-08-29 08:01:47 +02:00
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14d871730f x86jit: Optimize slow memory. 2023-08-28 21:16:38 -07:00
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8e8605935e irjit: Detect subtract-to-zero as constant. 2023-08-28 21:09:56 -07:00
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4e90bd5070 x86jit: Use NEG more automatically for Sub x,0,y. 2023-08-28 21:09:56 -07:00
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f263698897 irjit: Cleanup temp purging on exit. 
We were sometimes considering it read by exit and not purging.
 2023-08-27 12:26:05 -07:00
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552cd88938 irjit: Skip some work in PurgeTemps. 2023-08-20 08:59:47 -07:00
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57123e8f9e irjit: Reserve some arrays that churn. 
Improves IR compile time by around 20-30%.
 2023-08-20 08:59:47 -07:00
Henrik Rydgård
2cdcc413b7 Merge pull request #17898 from unknownbrackets/irjit-vfputemps 
irjit: Cleanup/purge FPU/VFPU temps
 2023-08-13 21:08:00 +02:00
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2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00