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41,472 Commits 54 Branches 120 Tags
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74 Commits

Author SHA1 Message Date
Nemoumbra
bd6c469543 Code-review fixes 2024-09-16 02:48:52 +03:00
Nemoumbra
f23b04fb4a Logic errors fixed + refactoring 2024-09-14 19:46:05 +03:00
Nemoumbra
34f113207d Added the MIPSTracer files to the project + name fix 2024-09-14 19:46:04 +03:00
Nemoumbra
a6be0517dc New IR instruction added 2024-09-14 19:46:04 +03:00
Henrik Rydgård
d3e6f19b6d Comments, log, cleanup 2024-07-22 01:15:35 +02:00
Henrik Rydgård
6ebec02f05 Fix crash in JITIR after disassembly improvement. 
Fixes #19292
 2024-06-22 15:16:27 +02:00
Henrik Rydgård
c9ca3904d3 Combine move-from-gpr and float cast. 2024-06-08 22:59:48 +02:00
Henrik Rydgård
0c246297d2 Create an IR op for a FPRtoGPR + shift-right-8, very common 2024-06-07 21:26:20 +02:00
Henrik Rydgård
d1e0384b2f Improve disasm 2024-06-07 19:32:37 +02:00
Henrik Rydgård
da88011805 Specialize a few arithmetic instructions for the interpreter. 2024-06-07 19:32:37 +02:00
Henrik Rydgård
a6f398a7d2 Add IRJit arena overflow check 2024-06-07 10:17:01 +02:00
Henrik Rydgård
d1a00f61de Improve disassembly of CallReplacement IR op 2024-06-06 15:24:58 +02:00
Henrik Rydgård
e3177ac870 Make some global string pointers const, not just the strings. 
Minor cleanup.
 2023-12-29 14:09:45 +01:00
Unknown W. Brackets
053831bf4d HLE: Add mechanics for sliced replacements. 2023-12-16 09:08:58 -08:00
Unknown W. Brackets
1042737c21 irjit: Correct metadata on Vec2 packing ops. 2023-09-03 21:13:11 -07:00
Unknown W. Brackets
e1a1f56f4c irjit: Cleanup breakpoint ops. 2023-09-03 12:27:10 -07:00
Unknown W. Brackets
f263698897 irjit: Cleanup temp purging on exit. 
We were sometimes considering it read by exit and not purging.
 2023-08-27 12:26:05 -07:00
Unknown W. Brackets
cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
79ca880ac7 irjit: Implement vqmul, add Vec4Blend. 
Should be useful more places.
 2023-08-06 13:38:00 -07:00
Unknown W. Brackets
b03398a46c Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
 2023-07-30 14:49:37 -07:00
Unknown W. Brackets
f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets
f3240393fa irjit: Use vf for vfpu regs, v0 is a gpr. 2023-07-30 14:16:17 -07:00
Unknown W. Brackets
6819acd29f irjit: Fix flag on float cond move. 2023-07-30 14:16:17 -07:00
Henrik Rydgård
180bda6f6b Merge pull request #17799 from unknownbrackets/irjit-lsu 
Add ll/sc to IR and x86jit
 2023-07-30 09:15:55 +02:00