Henrik Rydgård
e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
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52db66e7ad
riscv: Add vector bitmanip encoding.
2023-12-29 09:42:23 -08:00
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83dc1c9705
riscv: Add detect flags, not detected yet.
2023-12-29 09:42:23 -08:00
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e5467d2706
riscv: Add czero instruction encoding.
2023-12-29 09:42:23 -08:00
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e3c6add63a
riscv: Add encoding for Zcb.
2023-12-29 09:42:23 -08:00
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15cb782f85
riscv: Implement Zfa encoding.
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Not yet enabled/detected.
2023-12-29 09:42:23 -08:00
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fc476020ba
riscv: Improve immediate generation.
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Use compressed instructions more, better jumps when outside PC 32-bit
range.
2023-08-12 09:37:02 -07:00
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4b9011e475
riscv: Reduce call bloat using temps.
2023-08-08 23:17:32 -07:00
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26a527bdf8
riscv: Implement float/int conversion.
2023-07-30 00:45:51 -07:00
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76e3246065
riscv: Reduce jit codesize a bit.
2023-07-23 18:01:00 -07:00
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47b81985bd
riscv: Initial untested dispatcher.
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The minimum to actually, probably, running code. Pretty slow.
2023-07-23 18:01:00 -07:00
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030a27f15d
riscv: Stop considering bitmanip "B".
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Apparently it's not being called B anymore and B is still reserved.
2023-07-23 14:41:08 -07:00
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e0eace505b
riscv: Fix cases of SetRegToImmediate().
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Was using the wrong value for AUIPC, causing assertion failures and wrong
values. Also needed to handle sign-extend more carefully.
2023-07-23 14:41:08 -07:00
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27e60a9f2e
riscv: Sum weighted matrices in vertexjit.
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Not yet doing pos/norm, so not used yet.
2023-02-16 18:32:58 -08:00
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04ce3a0572
riscv: Allow subset of B extension to be used.
2023-02-16 16:09:22 -08:00
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684aa75388
riscv: Include morph in vertexjit.
2023-02-14 20:20:55 -08:00
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1ec33ddc04
riscv: Use __riscv_flush_icache() on Linux.
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This seems to perhaps clear icache on all harts. Otherwise crashing is
seen. Not sure what to do on other platforms.
2023-02-14 19:59:42 -08:00
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0b05d20c0a
riscv: Fix poison with compressed instructions.
2023-02-12 13:02:55 -08:00
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89c18d8077
riscv: Cleanup missing Poison, Crash.
2023-02-12 12:10:29 -08:00
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a0ef9ce103
riscv: Add half-float encodings.
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These are simple.
2023-01-29 16:31:01 -08:00
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dcd83c1e47
riscv: Detect Zicsr with cpu_features.
2023-01-29 15:24:41 -08:00
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3bc2450b5e
riscv: Add bitmanip instructions to emitter ( #16832 )
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* riscv: Cleanup emitter, add bitmanip detect.
Better to encode using Funct7::ZERO, and obviously for SRA.
* riscv: Add bitmanip instructions to emitter.
2023-01-22 21:37:47 +01:00
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2aeee83971
riscv: Add vector transfer instructions.
2023-01-22 00:17:40 -08:00
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c99eb18f33
riscv: Add vector mask instructions.
2023-01-21 23:43:28 -08:00
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88de043329
riscv: Add vector reduce instructions.
2023-01-21 22:35:38 -08:00
