Unknown W. Brackets
d40ac043d4
interp: Handle prefixes for Vmmov/Vmmul/Vmscl.
...
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
2019-03-31 10:37:07 -07:00
Unknown W. Brackets
26b1368f7b
interp: Handle vrot prefixes mostly correctly.
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Still some issues with 1/2 results and negate on swizzle.
2019-03-31 10:37:07 -07:00
Unknown W. Brackets
8fd8dce185
interp: Use a helper to generate prefix consts.
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This makes more logical sense that using the VFPU_SWIZZLE and VFPU_ABS
macros to select the constant, although that's how the bits work.
2019-03-31 10:33:26 -07:00
Unknown W. Brackets
b86a6af364
interp: Properly apply mask on single lane ops.
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When using something like vadd.s, we should still be applying the mask.
Mainly should only matter if masks are set in a conditional, or if games
nop out instructions.
2019-03-31 10:13:28 -07:00
Unknown W. Brackets
1936e8c4d1
interp: Generate constants using prefixes.
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This way they properly respect negate in the S prefix.
2019-03-31 10:13:28 -07:00
Unknown W. Brackets
0be3213151
interp: Correct vscl prefix handling.
2019-03-31 10:13:28 -07:00
Unknown W. Brackets
ec1dae57eb
interp: Fix vbfy prefix handling.
2019-03-31 10:09:18 -07:00
Unknown W. Brackets
d5273f589a
interp: Mask value in vpfxd.
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The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
2019-03-31 08:23:36 -07:00
Unknown W. Brackets
9d1d4473e8
interp: Confirm vi2f/vf2i prefix handling.
2019-03-31 08:22:52 -07:00
Unknown W. Brackets
30223cb17f
interp: Apply T prefix to D in vcmov.
2019-03-31 08:22:15 -07:00
Unknown W. Brackets
fef8e71b8f
interp: Correct behavior for matrixes with size=1.
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Games don't (shouldn't?) actually use 1x1 matrices, but they seem to have
predictable behavior in matrix ops.
2019-03-31 08:21:29 -07:00
Unknown W. Brackets
cfab70f149
interp: Handle abs/neg on nan values better.
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`fabsf` was altering other bits.
2019-03-31 08:18:49 -07:00
Unknown W. Brackets
7dc775e54f
IR: Use interp for unhandled prefix cases.
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The interpreter is not changed yet, so in theory this shouldn't change
behavior.
2019-03-31 08:17:11 -07:00
Unknown W. Brackets
4c3aa841d3
IR: Correct vmmul optimizations.
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It's a bit confusing since it's not D = S*T, but rather D = S'*T.
2019-03-23 15:31:10 -07:00
Unknown W. Brackets
aff1d8e8b2
interp: Implement vsbz and vlgb.
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Not sure any games actually use them, but good to have the remaining vfpu
ops all implemented.
2019-02-23 15:08:49 -08:00
Unknown W. Brackets
520f850e09
Jit: Correct VFPU prefix eating flags.
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Verified by tests. Also, confirmed that the old vxbz encoding had no
output, but the new position (as used by gas) does.
2019-02-23 15:08:49 -08:00
Unknown W. Brackets
179ec61815
interp: Correctly handle vsocp prefixes.
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Very similar to vsop, just with a bit more fixed values.
2019-02-23 10:05:13 -08:00
Unknown W. Brackets
6178a1fb33
Jit: Correct vocp prefix handling.
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See #5549 . Matches tests for various prefix settings.
2019-02-23 09:15:26 -08:00
Henrik Rydgård
c80dd44da8
ARM/ARM64: Ignore invalid immediate addresses in delay slots, which may be conditional.
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Should do something in x86's safe mem too, but leaving for later.
Replaces #11824
2019-02-23 10:15:09 +01:00
Unknown W. Brackets
d7f40afd9d
interp: Correct vocp prefix handling.
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Also, guess that vsocp also applies prefixes. See #5549 .
2019-02-21 19:02:16 -08:00
Henrik Rydgard
a802adb1f6
Add simple UI for JIT feature disable flags
2019-02-04 13:00:08 +01:00
Unknown W. Brackets
419c1fbd73
Jit: Respect flags for jit types and features.
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Left some free space for more.
2019-02-03 14:57:08 -08:00
Unknown W. Brackets
46649a218e
Core: Add flags to disable jit features.
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Not actually disabling yet, just setup.
2019-02-03 13:58:24 -08:00
pent0
4a53853f79
Update UWP port
2018-12-10 20:55:07 +07:00
Unknown W. Brackets
8506da14f0
Debugger: Prevent invalid address on syscall.
2018-11-17 08:54:29 -08:00
