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76 Commits

Author SHA1 Message Date
Unknown W. Brackets
59f491eddb x86jit: Micro optimize slt* a bit. 
This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.

Fixed a small mistake.
 2014-11-09 07:23:44 -08:00
Henrik Rydgard
5888b3bdc4 Revert "x86jit: Micro optimize slt* a bit." 
This reverts commit ee66596b8d.

Broke a lot of games, probably some small bug.

Conflicts:
	Core/MIPS/x86/CompALU.cpp
 2014-11-09 12:07:21 +01:00
Unknown W. Brackets
313d9e95c7 Clarify a comment. 2014-11-09 01:05:03 -08:00
Unknown W. Brackets
ee66596b8d x86jit: Micro optimize slt* a bit. 
This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.
 2014-11-08 22:54:03 -08:00
Henrik Rydgård
f99c2cd010 x86 Jit: Generate nicer code for some cases of addiu 2014-10-12 17:47:53 +02:00
Unknown W. Brackets
4a1514730f x86jit/ppcjit: Correct some bad sltiu compares. 2014-09-02 08:04:22 -07:00
Henrik Rydgard
82421f4dcf x86 jit: Further fix for nor, thanks unknown 
See #6638
 2014-07-27 22:26:35 +02:00
Henrik Rydgard
903ddbc513 x86 JIT: Fix bug where NOR would not get computed correctly in corner case 
(CompTriArith can end up not actually mapping rd to a register when taking
a shortcut)

May fix the JIT issue mentioned by CPkmn and located by daniel229 as an aside in #6638
 2014-07-27 21:41:41 +02:00
Unknown W. Brackets
27870aa593 x86jit: Map HI/LO as registers. 
Not actually ever cached, but now it's all consistent.
 2014-06-28 00:38:56 -07:00
Henrik Rydgård
aea272a3ce Jit x86: optimize "subu r, 0, r" to NEG r. 2014-03-03 13:42:32 +01:00
Unknown W. Brackets
2347498667 x86jit: Use templates to avoid some void * casts. 
Makes it a bit cleaner and potentially safer.
 2014-01-18 09:57:13 -08:00
Unknown W. Brackets
dffa35ef2f When ins is used with a zero argument, don't OR. 
Seems it's used effectively to mask out bits with rs=zero.  Makes sense...
 2013-11-29 09:17:12 -08:00
Unknown W. Brackets
fd38b10ab6 x86jit: Rename imm funcs to match armjit. 2013-11-10 21:59:49 -08:00
Unknown W. Brackets
3a8f0598c4 x86jit: Implement wsbh/wsbw. 2013-11-10 14:38:09 -08:00
Henrik Rydgard
5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Unknown W. Brackets
02dd250354 armjit: Optimize out a few immediate logic cases. 2013-11-08 11:39:24 -08:00
Unknown W. Brackets
97aa1a631e Improve typesafety in the x86 regalloc. 2013-08-24 19:41:10 -07:00
Unknown W. Brackets
109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
Unknown W. Brackets
3278b5e373 Handle the immediate case of clz/clo. 2013-07-04 23:07:42 -07:00
Unknown W. Brackets
654490566f Implement clz/clo in x86 jit. 2013-07-04 18:01:17 -07:00
Sacha
a26b48fc0b Stub wsbh/wsbw for x86. 2013-06-05 14:55:01 +10:00
Unknown W. Brackets
028e85dc92 Cleanup some differences between the two jits. 2013-03-07 02:08:44 -08:00
Unknown W. Brackets
313ffdb495 Add a stub for clz/clo in x86 jit. 2013-02-21 01:25:02 -08:00
Unknown W. Brackets
08923c092b Implement ins and ext in the x86 jit. 2013-02-21 01:25:01 -08:00
Unknown W. Brackets
dede852c03 Optimize out slti in the x86 jit. 
I'm kinda surprised this actually happens...
 2013-02-21 01:25:01 -08:00