Nemoumbra
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0faa1109d2
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Included <algorithm> for std::min
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2023-09-07 12:14:36 +03:00 |
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Unknown W. Brackets
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1b756ff8c1
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arm64jit: Add initial base for IR jit.
This works, but very slowly at this point.
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2023-09-03 12:14:28 -07:00 |
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Unknown W. Brackets
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2e64abd2a0
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x86jit: Improve some debug labels.
Helps when running a profiler that reads these.
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2023-08-27 12:51:29 -07:00 |
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Unknown W. Brackets
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08ea31f405
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x86jit: Improve debug disasm.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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c491f701ba
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x86jit: Add initial IR-based jit backend.
It works, but pretty slow in some parts with everything stubbed.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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4e41f83ecc
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riscv: Centralize IR reg cache metadata checks.
These are all largely the same between backends.
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2023-08-17 23:03:31 -07:00 |
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Unknown W. Brackets
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b30daa5760
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riscv: Centralize state of regcaches.
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2023-08-15 21:51:38 -07:00 |
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Unknown W. Brackets
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2bb67db43c
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riscv: Switch to the logBlocks model for disasm.
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2023-08-13 10:37:21 -07:00 |
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Unknown W. Brackets
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8c036a889d
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riscv: Add debug log of block disasm.
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2023-08-13 10:32:04 -07:00 |
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Unknown W. Brackets
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fcc90095f7
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riscv: Enable block linking.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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247788806a
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irjit: Add direct helper for start PC.
It's annoying always fetching length too.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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b3cdf06c5a
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riscv: Write fixup on block invalidation.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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3757ebca2d
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irjit: Invalidate/finalize target blocks.
Doesn't actually do anything yet, but adds plumbing.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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4b9011e475
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riscv: Reduce call bloat using temps.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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ad4cbbab8e
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riscv: Don't cache mipState on backend.
Bad sign if we're trying to use it, anyway.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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93e3d35f5d
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irjit: Move more to IRNativeBackend, split.
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2023-08-06 00:16:43 -07:00 |
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Unknown W. Brackets
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691799a0ca
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irjit: Centralize native jit compile dispatch.
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2023-08-03 23:14:58 -07:00 |
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Unknown W. Brackets
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c24dca12bb
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Build: Fix link issue for rv64 disasm.
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2023-07-30 16:06:55 -07:00 |
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Unknown W. Brackets
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b03398a46c
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Merge pull request #17815 from unknownbrackets/riscv-jit
riscv: Spill registers more intelligently
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2023-07-30 14:49:37 -07:00 |
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Unknown W. Brackets
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f870271011
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riscv: Spill registers more intelligently.
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2023-07-30 14:24:12 -07:00 |
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Unknown W. Brackets
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45d44c1d4f
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riscv: Implement block debug interface.
This gives us the target disasm in jit compare, bloat, etc.
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2023-07-30 14:21:43 -07:00 |
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Henrik Rydgård
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b93275bb35
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Merge pull request #17800 from unknownbrackets/riscv-jit
More RISC-V jit ops
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2023-07-30 09:26:22 +02:00 |
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Henrik Rydgård
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180bda6f6b
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Merge pull request #17799 from unknownbrackets/irjit-lsu
Add ll/sc to IR and x86jit
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2023-07-30 09:15:55 +02:00 |
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Unknown W. Brackets
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a5671bc716
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riscv: Add simple debug log of missed ops.
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2023-07-30 00:02:10 -07:00 |
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