16 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	4e3f3860f9	x86jit: Stub out op categories to files.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	f9bf7de701	riscv: Use a single reg cache.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	a23ade8f75	riscv: Map IR regs based on metadata. ... Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	fcc90095f7	riscv: Enable block linking.	2023-08-12 09:37:02 -07:00
Unknown W. Brackets	93e3d35f5d	irjit: Move more to IRNativeBackend, split.	2023-08-06 00:16:43 -07:00
Unknown W. Brackets	7071884a47	riscv: Handle rounding mode and ctrl transfers.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	a8edf5fa24	riscv: Reduce bloat in jit fallbacks.	2023-07-25 19:42:04 -07:00
Unknown W. Brackets	f7f7531500	riscv: Fix min/max normalization.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	34bfe93ea5	riscv: Fix block lookup issues.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	94be343591	riscv: Try to keep regs normalized, track. ... Since we can't address the lower 32-bits only in compares, this can help us avoid renormalizing before a compare.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	7aafa11d24	riscv: Implement conditional exits.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	720f868a10	riscv: Use R_RA as a temporary for calls. ... This is the most logical thing, since we're about to write it anyway.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	76e3246065	riscv: Reduce jit codesize a bit.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	624caa2dea	riscv: Implement the simplest exits.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00