15 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	0452b8b57a	riscv: Account for emuhack in JITBASEREG.	2023-09-03 13:29:05 -07:00
Unknown W. Brackets	f9bf7de701	riscv: Use a single reg cache.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	4b9011e475	riscv: Reduce call bloat using temps.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	ad4cbbab8e	riscv: Don't cache mipState on backend. ... Bad sign if we're trying to use it, anyway.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	93e3d35f5d	irjit: Move more to IRNativeBackend, split.	2023-08-06 00:16:43 -07:00
Unknown W. Brackets	c24dca12bb	Build: Fix link issue for rv64 disasm.	2023-07-30 16:06:55 -07:00
Unknown W. Brackets	f65b6fdb20	riscv: Remove incomplete block check. ... It shouldn't be necessary and bad things would happen anyway if it did.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	8d60c10a64	riscv: Use jit address offsets directly. ... We'll have IR able to use block number or target offset.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	7071884a47	riscv: Handle rounding mode and ctrl transfers.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	34bfe93ea5	riscv: Fix block lookup issues.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	5ed2f0d559	riscv: Implement logic ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	720f868a10	riscv: Use R_RA as a temporary for calls. ... This is the most logical thing, since we're about to write it anyway.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	1dfedde741	riscv: Avoid needless save/load around compile.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	4c1cc2dfdc	riscv: Add a register cache for jit. ... Not yet actually used. Might be buggy.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	47b81985bd	riscv: Initial untested dispatcher. ... The minimum to actually, probably, running code. Pretty slow.	2023-07-23 18:01:00 -07:00