Unknown W. Brackets
cc58d0d3a3
interp: Correct prefixes in vsrt ops.
2019-03-31 15:00:12 -07:00
Unknown W. Brackets
f2be0cb083
interp: Correct prefixes for vsbn/vsbz.
2019-03-31 13:52:59 -07:00
Unknown W. Brackets
175ceef583
interp: Cleanup vsocp size handling.
2019-03-31 13:52:07 -07:00
Unknown W. Brackets
4a2f8a74dc
interp: Correct size handling for vi2x ops.
2019-03-31 13:51:12 -07:00
Unknown W. Brackets
b75690787e
interp: Correct swizzle on vx2i ops.
2019-03-31 13:51:12 -07:00
Unknown W. Brackets
68cdcba6c5
interp: Don't write lane 2 on single colorconv.
...
Not that it's valid to use the op with that size anyway.
2019-03-31 13:51:12 -07:00
Unknown W. Brackets
5736b1be2a
interp: Correct some negative invalid zero cases.
...
In these cases, the input value wires to +0. Also, transposed the values
in a comment (oops.)
2019-03-31 13:45:37 -07:00
Unknown W. Brackets
aa998b815c
interp: Force vscmp result of invalid to zero.
...
Some other ops do this, but mostly only that do plus or minus.
2019-03-31 13:41:48 -07:00
Unknown W. Brackets
5749ae09d0
interp: Correct vmfvc register behavior.
...
The target and source registers were completely wrong.
2019-03-31 13:41:48 -07:00
Unknown W. Brackets
b2e024025f
interp: Handle wrong sizes of vf2h/vh2f.
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Probably not ever used, but they have consistent behavior.
2019-03-31 13:41:48 -07:00
Unknown W. Brackets
aceb0a8244
interp: Correct vrnd prefix handling.
...
We don't match random values perfectly anyway, but at least we should vary
at the right times.
2019-03-31 13:41:48 -07:00
Unknown W. Brackets
dfc2449f35
interp: Match actual vdiv prefix handling.
2019-03-31 13:41:48 -07:00
Unknown W. Brackets
af3ed69144
interp: Mask moves to vfpu ctrl.
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These bits of the registers can't be written.
2019-03-31 10:37:07 -07:00
Unknown W. Brackets
2a5d4e577d
interp: Handle NAN more correctly in vscmp.
2019-03-31 10:37:07 -07:00
Unknown W. Brackets
db28c61272
interp: Handle flush prefixes slightly better.
2019-03-31 10:37:07 -07:00
Unknown W. Brackets
d40ac043d4
interp: Handle prefixes for Vmmov/Vmmul/Vmscl.
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I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
2019-03-31 10:37:07 -07:00
Unknown W. Brackets
26b1368f7b
interp: Handle vrot prefixes mostly correctly.
...
Still some issues with 1/2 results and negate on swizzle.
2019-03-31 10:37:07 -07:00
Unknown W. Brackets
8fd8dce185
interp: Use a helper to generate prefix consts.
...
This makes more logical sense that using the VFPU_SWIZZLE and VFPU_ABS
macros to select the constant, although that's how the bits work.
2019-03-31 10:33:26 -07:00
Unknown W. Brackets
b86a6af364
interp: Properly apply mask on single lane ops.
...
When using something like vadd.s, we should still be applying the mask.
Mainly should only matter if masks are set in a conditional, or if games
nop out instructions.
2019-03-31 10:13:28 -07:00
Unknown W. Brackets
1936e8c4d1
interp: Generate constants using prefixes.
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This way they properly respect negate in the S prefix.
2019-03-31 10:13:28 -07:00
Unknown W. Brackets
0be3213151
interp: Correct vscl prefix handling.
2019-03-31 10:13:28 -07:00
Unknown W. Brackets
ec1dae57eb
interp: Fix vbfy prefix handling.
2019-03-31 10:09:18 -07:00
Unknown W. Brackets
d5273f589a
interp: Mask value in vpfxd.
...
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
2019-03-31 08:23:36 -07:00
Unknown W. Brackets
9d1d4473e8
interp: Confirm vi2f/vf2i prefix handling.
2019-03-31 08:22:52 -07:00
Unknown W. Brackets
30223cb17f
interp: Apply T prefix to D in vcmov.
2019-03-31 08:22:15 -07:00
