Unknown W. Brackets
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9439a43323
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riscv: Correct an overlap case, fix assert.
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2023-09-03 13:29:57 -07:00 |
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Unknown W. Brackets
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9bac755491
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x86jit: Avoid pointerify if clobbered.
For x86, it's not worth it for one.
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2023-09-01 22:34:22 -07:00 |
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Unknown W. Brackets
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d5a51da95e
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x86jit: Fix pointer modify when masked.
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2023-08-30 22:04:26 -07:00 |
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Unknown W. Brackets
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742dc0a0c7
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x86jit: Fix vec4 clobber issue.
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2023-08-30 22:04:25 -07:00 |
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Unknown W. Brackets
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1bfa054a41
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irjit: Correct GetFPRLaneCount().
Oops, this was just wrong...
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2023-08-28 21:09:56 -07:00 |
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Henrik Rydgård
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0ecfb6b112
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Merge pull request #17992 from unknownbrackets/x86-jit-float
x86jit: Implement trig instructions, couple other FPU
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2023-08-28 10:20:38 +02:00 |
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Unknown W. Brackets
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f10444eb42
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x86jit: Special case broadcast shuffles.
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2023-08-27 23:24:30 -07:00 |
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Unknown W. Brackets
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61a99b4bac
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x86jit: Implement trig/reciprocals.
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2023-08-27 23:24:30 -07:00 |
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Unknown W. Brackets
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7d8dc0f8ab
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irjit: Detect clobber in lane change.
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2023-08-27 12:27:05 -07:00 |
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Unknown W. Brackets
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d1a30334bf
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x86jit: Implement multiplies.
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2023-08-25 00:01:03 -07:00 |
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Unknown W. Brackets
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363f2b68e1
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x86jit: Implement shifts.
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2023-08-25 00:01:03 -07:00 |
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Unknown W. Brackets
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efaf14a19f
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x86jit: Fix spilling zero register.
We can't flush it, but it's likely not to get "clobbered".
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2023-08-22 23:29:13 -07:00 |
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Unknown W. Brackets
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c397e2e4da
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x86jit: Flush reg if dirty on map as ptr.
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2023-08-22 23:29:13 -07:00 |
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Unknown W. Brackets
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edcb156897
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x86jit: Add Vec4 and Float load/store.
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2023-08-22 10:39:46 +02:00 |
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Unknown W. Brackets
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07fa1ed573
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x86jit: Automatically flush incompatible regs.
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2023-08-21 21:16:54 -07:00 |
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Unknown W. Brackets
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db34b85107
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irjit: Allow flag-based allocation order.
Sometimes backends have needs, like XMM0/v0-only, or similar.
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2023-08-21 20:46:05 -07:00 |
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Unknown W. Brackets
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5045cf012e
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x86jit: Fix flushing of zero register.
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2023-08-20 22:28:54 -07:00 |
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Henrik Rydgård
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629d46ef5b
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Merge pull request #17938 from unknownbrackets/riscv-centralize
Centralize IR regcache from RISC-V
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2023-08-20 23:47:02 +02:00 |
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Unknown W. Brackets
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36b6aa4728
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riscv: Allow GPR "SIMD" without FPR SIMD.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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6a75e6712e
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riscv: Use automapping for special cases too.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a190793ad2
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riscv: Simplify mapping for more instructions.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e40ae60029
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riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a23ade8f75
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riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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32d8f6196f
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irjit: Cut time flushing imm regs.
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2023-08-20 08:59:47 -07:00 |
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