Commit Graph

60 Commits

Author SHA1 Message Date
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1042737c21 irjit: Correct metadata on Vec2 packing ops. 2023-09-03 21:13:11 -07:00
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e1a1f56f4c irjit: Cleanup breakpoint ops. 2023-09-03 12:27:10 -07:00
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f263698897 irjit: Cleanup temp purging on exit.
We were sometimes considering it read by exit and not purging.
2023-08-27 12:26:05 -07:00
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cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
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2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg.
We already have a zero reg, so this is more useful and symmetrical.
2023-08-13 10:40:47 -07:00
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79ca880ac7 irjit: Implement vqmul, add Vec4Blend.
Should be useful more places.
2023-08-06 13:38:00 -07:00
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b03398a46c Merge pull request #17815 from unknownbrackets/riscv-jit
riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
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f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
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f3240393fa irjit: Use vf for vfpu regs, v0 is a gpr. 2023-07-30 14:16:17 -07:00
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6819acd29f irjit: Fix flag on float cond move. 2023-07-30 14:16:17 -07:00
Henrik Rydgård
180bda6f6b Merge pull request #17799 from unknownbrackets/irjit-lsu
Add ll/sc to IR and x86jit
2023-07-30 09:15:55 +02:00
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e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. 2023-07-29 18:30:15 -07:00
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a5a2671af3 irjit: Implement vf2ix.
Used in LittleBigPlanet when playing intro movies.
2023-07-29 18:01:08 -07:00
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df2462b1d9 irjit: Implement ll/sc.
These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
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df313bd296 riscv: Fix rounding mode setting. 2023-07-25 20:33:56 -07:00
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9157d992ac jit-ir: Implement cfc1/ctc1.
This makes it so we can track rounding mode changes.
2023-07-25 20:33:56 -07:00
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6da10463f9 Debugger: Make reg names safer, stop using v000.
Better to use S000, etc. as that's more clear throughout.
2023-04-29 09:48:33 -07:00
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6715f41410 irjit: Add constructs for validing mem access.
Basically to allow slow/fast memory to work with IR, including for
alignment checks.
2022-08-21 13:01:23 -07:00
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021f4adfad irjit: Fix mtv for INF4. 2021-01-09 12:43:50 -08:00
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670334bd0c irjit: Correct flags for SetCtrlVFPUReg.
Fixes #13897.  Caused the reg to be optimized out.
2021-01-09 12:33:08 -08:00
Henrik Rydgård
3322adbc22 IR Interpreter: Add some missing instruction metadata. May help part of #10897 2018-04-11 11:16:41 +02:00
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6dda053365 irjit: Add dedicated ops for lwl/swl and friends.
Temporarily removes optimizations.
2018-01-07 21:05:57 -08:00
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bc541bd020 irjit: Encode downcount directly as a constant.
Simpler this way, now.
2018-01-03 23:32:31 -08:00
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cffb2d61a7 irjit: Embed constant inside IRInst.
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
2018-01-03 23:24:04 -08:00
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671be24105 irjit: Add extra temps to make lwl/swl/etc. easier. 2018-01-01 08:38:11 -08:00