Henrik Rydgård
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b346142df8
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Merge pull request #11954 from unknownbrackets/vfpu-chunk5
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
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2019-04-01 17:12:03 +02:00 |
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Unknown W. Brackets
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b24f84d1a2
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interp: Handle prefixes on matrix init ops.
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2019-03-31 17:11:24 -07:00 |
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Unknown W. Brackets
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59905de719
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interp: Correct vsgn out of swizzle bounds.
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2019-03-31 17:10:51 -07:00 |
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Unknown W. Brackets
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b881a689c4
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interp: Ignore high bit in vmfvc/vmtvc.
Both 0 and 128 read/write the S prefix, for example.
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2019-03-31 17:09:55 -07:00 |
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Unknown W. Brackets
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175ceef583
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interp: Cleanup vsocp size handling.
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2019-03-31 13:52:07 -07:00 |
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Unknown W. Brackets
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4a2f8a74dc
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interp: Correct size handling for vi2x ops.
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2019-03-31 13:51:12 -07:00 |
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Unknown W. Brackets
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b75690787e
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interp: Correct swizzle on vx2i ops.
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2019-03-31 13:51:12 -07:00 |
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Unknown W. Brackets
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68cdcba6c5
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interp: Don't write lane 2 on single colorconv.
Not that it's valid to use the op with that size anyway.
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2019-03-31 13:51:12 -07:00 |
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Unknown W. Brackets
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5749ae09d0
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interp: Correct vmfvc register behavior.
The target and source registers were completely wrong.
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2019-03-31 13:41:48 -07:00 |
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Unknown W. Brackets
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b2e024025f
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interp: Handle wrong sizes of vf2h/vh2f.
Probably not ever used, but they have consistent behavior.
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2019-03-31 13:41:48 -07:00 |
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Unknown W. Brackets
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af3ed69144
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interp: Mask moves to vfpu ctrl.
These bits of the registers can't be written.
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2019-03-31 10:37:07 -07:00 |
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Unknown W. Brackets
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d40ac043d4
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interp: Handle prefixes for Vmmov/Vmmul/Vmscl.
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
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2019-03-31 10:37:07 -07:00 |
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Unknown W. Brackets
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ec1dae57eb
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interp: Fix vbfy prefix handling.
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2019-03-31 10:09:18 -07:00 |
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Unknown W. Brackets
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d5273f589a
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interp: Mask value in vpfxd.
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
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2019-03-31 08:23:36 -07:00 |
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Unknown W. Brackets
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7dc775e54f
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IR: Use interp for unhandled prefix cases.
The interpreter is not changed yet, so in theory this shouldn't change
behavior.
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2019-03-31 08:17:11 -07:00 |
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Unknown W. Brackets
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4c3aa841d3
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IR: Correct vmmul optimizations.
It's a bit confusing since it's not D = S*T, but rather D = S'*T.
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2019-03-23 15:31:10 -07:00 |
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Unknown W. Brackets
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6178a1fb33
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Jit: Correct vocp prefix handling.
See #5549. Matches tests for various prefix settings.
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2019-02-23 09:15:26 -08:00 |
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Unknown W. Brackets
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d7f40afd9d
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interp: Correct vocp prefix handling.
Also, guess that vsocp also applies prefixes. See #5549.
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2019-02-21 19:02:16 -08:00 |
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Unknown W. Brackets
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419c1fbd73
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Jit: Respect flags for jit types and features.
Left some free space for more.
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2019-02-03 14:57:08 -08:00 |
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Henrik Rydgård
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34f79904fd
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IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily.
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2018-01-10 09:19:27 +01:00 |
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Henrik Rydgård
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18be23eccc
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IR: More fixes. Still something wrong with VFPU compares (not caused by this PR).
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2018-01-04 19:38:36 +01:00 |
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Henrik Rydgård
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1a97f62dc9
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Fix running the CPU test from the UI.
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2018-01-04 18:10:41 +01:00 |
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Unknown W. Brackets
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905d2c2da6
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irjit: Cleanup some invalid op handling.
And log blocks the same way as other backends.
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2018-01-01 08:38:11 -08:00 |
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Henrik Rydgård
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22e65ba80d
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Get rid of ugly alignment macros and some other cruft, we now have alignas(16) from C++11
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2017-08-31 01:14:51 +02:00 |
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Unknown W. Brackets
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b483444fab
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IR: Cleanup some invalid ops.
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2017-04-20 21:11:40 -07:00 |
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